Abstract: The throughput of a network appliance can be increased by a circuit that produces an encrypted block and a digest value while requiring only a single read of a data block. Data blocks, including a first data block, are stored in a memory that can be accessed by an ASIC that includes an encryption offload circuit. The ASIC can read the first data block from the memory and the encryption offload circuit can produce a first encrypted block and a first digest value from the first data block. The ASIC can produce a network packet that includes the first encrypted block and a data digest value. The first digest value is used to produce the data digest value, and a single read of the first data block from the memory is performed for producing the first encrypted block and also for calculating the first digest value.

Abstract: Presented herein are techniques for performing packet forwarding or routing using a pipeline of a plurality of tiles. A method includes receiving a packet, parsing the packet to generate a vector, passing the vector to a first tile dedicated to a first type of lookup, performing a lookup in the first tile, storing a result of the first type of lookup in the vector to obtain a first updated vector, passing the first updated vector to a second tile dedicated to a second type of lookup, performing a lookup in the second tile, storing a result of the second type of lookup in the vector to obtain a second updated vector, and transmitting the packet from the network routing device via an output port thereof selected based on the second updated vector.

Abstract: Systems, methods, and computer-readable media for improving debugging and troubleshooting of datacenter networks, and more particularly improving the speed of forwarding/data path related problems without going into ASIC level debugging. A switch could, for example, have a processor which communicates with an ASIC. The processor can receive flow information and a notification from the ASIC, the notification indicating a predefined error condition has been identified in a packet. The processor can modify the ASIC programming based on the notification, such that the ASIC records additional, more-detailed, flow information for the switch. The processor can then receive, from the modified ASIC, the additional flow information. The additional flow information can then be used (either by the processor or by an operator) to identify the exact reason for the errors in the flow path.

Abstract: Presented herein are techniques for performing packet forwarding or routing using a pipeline of a plurality of tiles. A method includes receiving a packet, parsing the packet to generate a vector, passing the vector to a first tile dedicated to a first type of lookup, performing a lookup in the first tile, storing a result of the first type of lookup in the vector to obtain a first updated vector, passing the first updated vector to a second tile dedicated to a second type of lookup, performing a lookup in the second tile, storing a result of the second type of lookup in the vector to obtain a second updated vector, and transmitting the packet from the network routing device via an output port thereof selected based on the second updated vector.

Abstract: Systems, methods, and computer-readable media for improving debugging and troubleshooting of datacenter networks, and more particularly improving the speed of forwarding/data path related problems without going into ASIC level debugging. A switch could, for example, have a processor which communicates with an ASIC. The processor can receive flow information and a notification from the ASIC, the notification indicating a predefined error condition has been identified in a packet. The processor can modify the ASIC programming based on the notification, such that the ASIC records additional, more-detailed, flow information for the switch. The processor can then receive, from the modified ASIC, the additional flow information. The additional flow information can then be used (either by the processor or by an operator) to identify the exact reason for the errors in the flow path.

Abstract: According to one aspect, a method includes determining whether at least one memory storage unit in a first stage of a multi-stage array is available for use by a first counter associated with the first stage, and allocating the at least one memory storage unit for use by the first counter when the at least one memory storage unit is available. When the at least one memory storage unit is not available for use by the first counter, the method includes identifying a second counter stored in a first location in the first stage, the first location including a first memory storage unit and a second memory storage unit, and moving the second counter to a second stage of the multi-stage array, storing a pointer to the second stage in the first memory storage unit, and allocating the second memory storage unit to the first counter.

Abstract: According to one aspect, a method includes determining whether at least one memory storage unit in a first stage of a multi-stage array is available for use by a first counter associated with the first stage, and allocating the at least one memory storage unit for use by the first counter when the at least one memory storage unit is available. When the at least one memory storage unit is not available for use by the first counter, the method includes identifying a second counter stored in a first location in the first stage, the first location including a first memory storage unit and a second memory storage unit, and moving the second counter to a second stage of the multi-stage array, storing a pointer to the second stage in the first memory storage unit, and allocating the second memory storage unit to the first counter.

Abstract: An example method, system, and switching element are provided and may provide for an egress port to be configured to receive a plurality of data packets, each of the plurality of data packets being a class of a plurality of classes. A buffer may communicate with the at least one data port interface. A memory management unit may be configured to enable and disable transmission of the plurality of classes of the plurality of data packets based on a metering policy; and place the plurality of data packets in the buffer.

Abstract: An example method, system, and switching element are provided and may provide for an egress port to be configured to receive a plurality of data packets, each of the plurality of data packets being a class of a plurality of classes. A buffer may communicate with the at least one data port interface. A memory management unit may be configured to enable and disable transmission of the plurality of classes of the plurality of data packets based on a metering policy; and place the plurality of data packets in the buffer.