Abstract: A method for detecting image information includes: acquiring at least one sample of image pair to be processed; calculating a reconstruction loss function of the second feature extraction model based on the first image samples and the first reconstructed image feature information; calculating an adversarial loss function of the third feature extraction model based on the second reconstructed image feature information and the first image samples; optimizing the first model parameters in the first feature extraction model based on the reconstruction and the adversarial loss function to generate the optimized first feature extraction model; inputting the acquired image pair to be processed into the optimized first feature extraction model to generate the difference information. The method reduces the first feature extraction model's dependence on the labeled data and improves the model's recognition efficiency and accuracy by using the samples without the labeled difference information.

Abstract: A packaged cavity structure includes an embedded packaging frame having a first cavity and a first conductive post respectively penetrating an insulation layer in a height direction, a chipset within the first cavity, a first circuit layer on an upper surface of the embedded packaging frame, a first dielectric layer on the first circuit layer, a second circuit layer on the first dielectric layer, a through-hole penetrating the first dielectric layer and the insulation layer, a third circuit layer on a lower surface of the embedded packaging frame, a support post enclosure on the third circuit layer, and a packaging layer formed along the outside of the support post enclosure. A second cavity communicating with the through-hole is formed between the packaging layer and the lower surface of the embedded packaging frame, and the chipset includes a first chip and a second chip provided in a back-to-back stack.

Abstract: A chip high-density interconnection package structure includes a plate having a groove and a glass frame, a first via post penetrating the glass frame, a second via post penetrating the groove, a first line layer and a second line layer on the glass frame and electrically connected via the first via post, a third line layer and a fourth line layer on the groove and electrically connected via the second via post, a chip connection bridge on the third line layer in the groove, and a fifth line layer on the first line layer, and chips on the second line layer and the fourth line layer. The chip connection bridge has a first pad connected to the third line layer, the terminals of the two chips are connected to the fourth line layer and/or the second line layer, and the fifth line layer is connected to the first line layer.

Abstract: A method for manufacturing a high-heat-dissipation mixed substrate includes: preparing a mother substrate, the mother substrate including an insulating layer and a temporary carrier plate which are laminated; arranging a plurality of first grooves and a plurality of first cavities on the mother substrate; filling the first groove with a thermally-conductive material to form a first thermally-conductive block, and adhering an embedded device in the first cavity and filling the first cavity with the thermally-conductive material to form a second thermally-conductive block; removing the temporary carrier plate to obtain a semi-finished substrate; manufacturing circuit layers on two opposite side surfaces of the semi-finished substrate to obtain a target mother substrate; and cutting the target mother substrate along region dividing lines to obtain a mixed substrate with a side surface being a thermally-conductive surface.

Abstract: A manufacturing method for an embedded flip chip package substrate includes laminating a first dielectric layer on the first line layer formed on a carrier plate, forming a first window on the first dielectric layer, filling a first copper post in the first window, forming a second window on the first dielectric layer, mounting a flip chip to the second window, sequentially stacking a packaging layer and a second dielectric layer covered with a first metal layer on the first dielectric layer, pressing a packaging layer encapsulating the first copper post and the flip chip and a second dielectric layer, curing the packaging layer, opening a hole through the first metal layer, the second dielectric layer and the packaging layer to form an interlayer conducting blind hole, forming a second line layer on the first metal layer, and removing the carrier plate to obtain a package substrate.

Abstract: A method for manufacturing a structure for embedding and packaging multiple devices by layer includes preparing a polymer supporting frame, mounting a first device in a first device placement mouth frame to form a first packaging layer, forming a first circuit layer and a second circuit layer, forming a second conductive copper pillar layer and a second sacrificial copper pillar layer, forming a second insulating layer on the first circuit layer, and forming a third insulating layer on the second circuit layer, forming a second device placement mouth frame vertically overlapped with the first device placement mouth frame, mounting a second device and a third device in the second device placement mouth frame to form a second packaging layer, forming a third circuit layer on the second insulating layer. A terminal of the second device and a terminal of the third device are respectively communicated with the third circuit layer.

Abstract: A package substrate with an embedded device and a manufacturing method therefor are disclosed. The method includes: manufacturing a third circuit layer and a target on a temporary carrier plate, and laminating a third dielectric layer; placing a device to be embedded on the third dielectric layer which is then covered with a second dielectric layer; laminating a second copper foil and manufacturing a second circuit layer, a second copper pillar, and a third copper pillar; laminating a first dielectric layer and a first copper foil sequentially, and removing the temporary carrier plate; laminating a fourth dielectric layer on the third circuit layer; laminating a fourth copper foil on the fourth dielectric layer; and manufacturing a fourth circuit layer and a fourth copper pillar through the fourth copper foil, and manufacturing a first circuit layer and a first copper pillar through the first copper foil.

Abstract: A multichip interconnecting packaging structure includes a glass frame, a first line layer and a second line layer respectively provided on the first surface and the second surface of the glass frame, a first via post penetrating through the glass frame, a cavity penetrating through the glass frame, a chip connecting device embedded in the cavity, a first insulating layer filling the cavity to cover the chip connecting device, and a first chip and a second chip provided on the surface of the first line layer, wherein a terminal of the chip connecting device is connected to the first line layer, the first line layer and the second line layer are in conductive communication through the first via post, the first chip and the second chip are connected to the chip connecting device through the first line layer to interconnect the first chip with the second chip.

Abstract: A packaging structure for realizing chip interconnection includes a core layer, a bridging layer, a first dielectric layer, a second dielectric layer, a first bonding pad layer and a second bonding pad layer. The first dielectric layer is arranged between the core layer and the first bonding pad layer, the second dielectric layer is arranged between the second bonding pad layer and the core layer. The first bonding pad layer is connected with the core layer through a first via, the second bonding pad layer is connected with the core layer through a second via. The bridging layer is embedded in the first dielectric layer. The bridging layer is electrically insulated from the core layer, and the bridging layer is connected with the first bonding pad layer through a third via.

Abstract: A liquid circulating cooling package substrate includes a circulating cooling structure including a cooling chamber in a first dielectric layer to expose a heat dissipation face, a metal heat dissipation layer on the inner surface of the cooling chamber, an upright support column formed on a metal heat dissipation layer, and a cooling cover supported on the support column to close the cooling chamber along the periphery of the cooling chamber. The metal heat dissipation layer completely covers the heat dissipation face and the inner side surface of the cooling chamber, and a liquid inlet and a liquid outlet are formed on the cooling cover. A circulating cooling structure is provided in the first dielectric layer, and the circulating cooling structure is formed during the processing of an embedded package substrate such that the processing flow is simple and the cost is low.

Abstract: A manufacturing method for a substrate embedded with integrated inductor includes: providing a bearing plate; manufacturing a first conduction copper column on the bearing plate; arranging a first dielectric layer on the bearing plate which covers the first conduction copper column; opening the first dielectric layer to form a first opening; filling a magnetic material at the first opening; grinding the first dielectric layer so that surfaces of the first conduction copper column and the magnetic material are flush with a surface of the first dielectric layer; removing the bearing plate, etching a metal layer on the surface of the first dielectric layer to form a package substrate; arranging a first circuit layer and a solder mask layer on an upper surface and a lower surface of the package substrate; and forming a window in the solder mask layer corresponding to the first circuit layer.

Abstract: A manufacturing method for a conductive substrate with a filtering function includes preparing a core layer and forming first and second conductive holes in the core layer, forming a sacrificial copper layer on the first conductive hole and on the core layer, forming a metal layer on the second conductive hole, forming a metal post in the first conductive hole, forming a lower insulating layer on the core layer, forming a lower insulative post in the second conductive hole, forming a magnet wrapping around the metal post to obtain a first conductive post, forming an upper insulating layer on the core layer, forming an upper insulative post in the second conductive hole to obtain a second conductive post, removing the upper insulating layer, the lower insulating layer, and the remaining sacrificial copper post layer, followed by flattening.

Abstract: A carrier plate for preparing a package substrate according to an embodiment includes a dielectric layer, a seed layer in the dielectric layer, and a copper pillar layer on the seed layer. A bottom end of the seed layer is higher than a lower surface of the dielectric layer. A top end of the copper pillar layer is lower than an upper surface of the dielectric layer. The upper and lower surfaces of the dielectric layer are respectively provided with a first metal layer and a second metal layer.

Abstract: A packaging structure includes multiple packaging units, and the packaging units include a hard plate region, a winding region, and a fan-out region. In the packaging structure, the hard plate region of the packaging unit is arranged in a stacked manner, some or all of the fan-out regions are packaged with a chip, and some or all of the fan-out regions packaged with a chip are stacked with the hard plate regions after being bent by the winding region. So designed, each fan-out region is individually packaged and then packaged by stacking with each other to achieve the interconnections between a chip and a chip, and between a chip and a substrate without interference between the packaging units.

Abstract: A package substrate and a manufacturing method thereof are disclosed. The method includes: providing an inner substrate; processing an adhesive photosensitive material on a surface of a first side of the inner substrate to obtain an adhesive first insulating dielectric layer; mounting a component on the first insulating dielectric layer; and processing a photosensitive packaging material on the first side of the inner substrate to obtain a second insulating dielectric layer, where the second insulating dielectric layer covers the component.

Abstract: A method for manufacturing a packaging substrate, and a packaging substrate are disclosed. The method includes: providing a bottom board with a first circuit layer, the first circuit layer being provided with at least one demand point, and one side of the demand point being provided with a first to-be-avoided region; machining a first intermediate insulating layer on the bottom board, the first intermediate insulating layer including a first intermediate insulating dielectric covering the first to-be-avoided region; machining a first intermediate wiring layer on the first intermediate insulating layer, the first intermediate wiring layer including a first intermediate circuit partially arranged on the first intermediate insulating dielectric and connected to the demand point; machining a first insulating layer on the first intermediate wiring layer which is stacked on the bottom board and covers the first intermediate wiring layer; and machining a circuit build-up layer on the first insulating layer.

Abstract: A method for manufacturing a structure for embedding and packaging multiple devices by layer includes preparing a polymer supporting frame, mounting a first device in a first device placement mouth frame to form a first packaging layer, forming a first circuit layer and a second circuit layer, forming a second conductive copper pillar layer and a second sacrificial copper pillar layer, forming a second insulating layer on the first circuit layer, and forming a third insulating layer on the second circuit layer, forming a second device placement mouth frame vertically overlapped with the first device placement mouth frame, mounting a second device and a third device in the second device placement mouth frame to form a second packaging layer, forming a third circuit layer on the second insulating layer. A terminal of the second device and a terminal of the third device are respectively communicated with the third circuit layer.

Abstract: An embedded inductance structure includes an insulating layer, an inductance located in the insulating layer, a multi-layer conducting circuit located in the insulating layer and on the upper surface and lower surface of the insulating layer, and a multi-layer conductive copper column layer located in the insulating layer. The inductance and the multi-layer conducting circuit are conductively connected via the multi-layer conductive copper column layer, and the inductance includes a magnet and an inductance coil in direct contact with the magnet, and the inductance coil is composed of a multi-layer conductive coil and a conductive copper column located between adjacent conductive coils. The multi-layer conductive coils are respectively in a ring shape with a notch and are disconnected at the notch, and the positions of the conductive copper columns located on the upper side and lower of each conductive coil are different in the longitudinal direction.

Abstract: A robot joint torque control system and a load compensation method therefor are provided, which relate to the technical field of robot joint motion control. A mathematical model of the robot joint torque control system is established first. Equivalent transformation is performed on a system functional block diagram thereof, and then it can be seen that load parameters have a great influence on joint torque output. A load compensation controller is designed to effectively eliminate the influence of the load parameters on an output torque of the joint. The system is equivalent to an inertial element on the basis of the compensation, and then a PD controller parameter is adjusted to increase an open-loop gain of the system, so as to increase a system bandwidth and increase a response speed of the joint torque control system, thereby improving performance of the joint torque control system.

Abstract: An embedded packaging structure and a manufacturing method thereof are disclosed. The method includes: providing a bearing plate with a first metal seed layer; processing on the first metal seed layer to obtain a substrate; removing the bearing plate to obtain the substrate, and processing on the substrate to obtain a first and a second cavities penetrating therethrough; assembling a first component in the first cavity, assembling a connecting flexible board in the second cavity, processing on a second side of the substrate to obtain a second insulating layer; processing on a first side of the substrate to obtain a second circuit layer, assembling a second component on the second circuit layer; bending the substrate through the connecting flexible board to form an included angle less than 180 degrees on the first side, and packaging the first side by using a packaging material to obtain a packaging layer.