Patents by Inventor Gaobo Xu

Gaobo Xu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9899270
    Abstract: There is disclosed a method for manufacturing a semiconductor device comprising two opposite types of MOSFETs formed on one semiconductor substrate, the method comprising: forming a portion of the MOSFET on the semiconductor substrate, said portion of said MOSFET comprising source/drains regions located in the semiconductor substrate, a dummy gate stack located between the source/drain region and above the semiconductor substrate and a gate spacer surrounding the dummy gate stack; removing the dummy gate stack of said MOSFET to form a gate opening which exposes the surface of the semiconductor substrate; forming an interfacial oxide layer on the exposed surface of the semiconductor structure; forming a high-K gate dielectric on the interfacial oxide layer within the gate opening; forming a first metal gate layer on the high-K gate dielectric; implanting doping ions in the first metal gate layer; forming a second metal gate layer on the first metal gate layer to fill up the gate opening; and annealing to diffu
    Type: Grant
    Filed: December 7, 2012
    Date of Patent: February 20, 2018
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Qiuxia Xu, Huilong Zhu, Gaobo Xu, Huajie Zhou, Qingqing Liang, Dapeng Chen, Chao Zhao
  • Patent number: 9252059
    Abstract: A method for manufacturing a semiconductor device that comprises two opposite types of MOSFETs formed on one semiconductor substrate, comprising: defining an active region for each of the MOSFETs on the semiconductor substrate; forming an interfacial oxide layer on a surface of the semiconductor substrate; forming a high-K gate dielectric layer on the interfacial oxide layer; forming a metal gate layer on the high-K gate dielectric layer; implanting dopant ions in the metal gate layer; forming a Poly-Si layer on the metal gate layer; patterning the Poly-Si layer, the metal gate layer, the high-K gate dielectric layer and the interfacial oxide layer to form a plurality of gate stack structures; forming a plurality of gate spacer surrounding each of the plurality of gate stack structures; and forming a plurality of S/D regions.
    Type: Grant
    Filed: December 7, 2012
    Date of Patent: February 2, 2016
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Qiuxia Xu, Gaobo Xu, Huajie Zhou, Huilong Zhu, Dapeng Chen
  • Patent number: 9196706
    Abstract: Provided is a method for manufacturing a p-type MOSFET, including: forming a part of the MOSFET on a semiconductor substrate including source/drain regions, a replacement gate, and a gate spacer; removing the replacement gate stack of the MOSFET to form a gate opening; forming an interface oxide layer on the exposed surface of the semiconductor substrate; forming a high-K gate dielectric layer on the interface oxide layer; forming a first metal gate layer; implanting dopant ions into the first metal gate layer; and performing annealing to cause the dopant ions to diffuse and accumulate at an upper interface between the high K gate dielectric layer and the first metal gate layer and a lower interface between the high-K gate dielectric layer and the interface oxide layer, and also to generate electric dipoles by interfacial reaction at the lower interface between the high-K gate dielectric layer and the interface oxide layer.
    Type: Grant
    Filed: December 7, 2012
    Date of Patent: November 24, 2015
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Qiuxia Xu, Huilong Zhu, Tianchun Ye, Huajie Zhou, Gaobo Xu, Qingqing Liang
  • Publication number: 20150325684
    Abstract: A method for manufacturing an NMOSFET may comprise: defining an active region for the NMOSFET on a semiconductor substrate; forming an interfacial oxide layer on a surface of the semiconductor substrate; forming a high-K gate dielectric layer on the interfacial oxide layer; forming a metal gate layer on the high-K gate dielectric layer; implanting dopant ions into the metal gate layer; forming a Poly-Si layer on the metal gate layer; patterning the Poly-Si layer, the metal gate layer, the high-K gate dielectric layer and the interfacial oxide layer to form a gate stack; forming a gate spacer surrounding the gate stack; and forming source and drain regions.
    Type: Application
    Filed: December 7, 2012
    Publication date: November 12, 2015
    Inventors: Qiuxia Xu, Gaobo Xu, Huajie Zhou, Huilong Zhu
  • Publication number: 20150295067
    Abstract: The present disclosure discloses a method for manufacturing a P-type MOSFET, comprising: forming a part of the MOSFET on a semiconductor substrate, the part of the MOSFET comprising source/drain regions in the semiconductor substrate, a replacement gate stack between the source/drain regions above the semiconductor substrate, and a gate spacer surrounding the replacement gate stack; removing the replacement gate stack of the MOSFET to form a gate opening exposing a surface of the semiconductor substrate; forming an interface oxide layer on the exposed surface of the semiconductor; forming a high-K gate dielectric layer on the interface oxide layer in the gate opening; forming a first metal gate layer on the high-K gate dielectric layer; implanting dopant ions into the first metal gate layer; and performing annealing to cause the dopant ions to diffuse and accumulate at an upper interface between the high-K gate dielectric layer and the first metal gate layer and a lower interface between the high-K gate diele
    Type: Application
    Filed: December 7, 2012
    Publication date: October 15, 2015
    Applicant: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Qiuxia Xu, Huilong Zhu, Huajie Zhou, Gaobo Xu, Qingqing Liang
  • Publication number: 20150279745
    Abstract: There is disclosed a method for manufacturing a semiconductor device comprising two opposite types of MOSFETs formed on one semiconductor substrate, the method comprising: forming a portion of the MOSFET on the semiconductor substrate, said portion of said MOSFET comprising source/drains regions located in the semiconductor substrate, a dummy gate stack located between the source/drain region and above the semiconductor substrate and a gate spacer surrounding the dummy gate stack; removing the dummy gate stack of said MOSFET to form a gate opening which exposes the surface of the semiconductor substrate; forming an interfacial oxide layer on the exposed surface of the semiconductor structure; forming a high-K gate dielectric on the interfacial oxide layer within the gate opening; forming a first metal gate layer on the high-K gate dielectric; implanting doping ions in the first metal gate layer; forming a second metal gate layer on the first metal gate layer to fill up the gate opening; and annealing to diffu
    Type: Application
    Filed: December 7, 2012
    Publication date: October 1, 2015
    Inventors: Qiuxia Xu, Huilong Zhu, Gaobo Xu, Huajie Zhou, Qingqing Liang, Dapeng Chen, Chao Zhao
  • Publication number: 20150262887
    Abstract: A method for manufacturing a semiconductor device that comprises two opposite types of MOSFETs formed on one semiconductor substrate, comprising: defining an active region for each of the MOSFETs on the semiconductor substrate; forming an interfacial oxide layer on a surface of the semiconductor substrate; forming a high-K gate dielectric layer on the interfacial oxide layer; forming a metal gate layer on the high-K gate dielectric layer; implanting dopant ions in the metal gate layer; forming a Poly-Si layer on the metal gate layer; patterning the Poly-Si layer, the metal gate layer, the high-K gate dielectric layer and the interfacial oxide layer to form a plurality of gate stack structures; forming a plurality of gate spacer surrounding each of the plurality of gate stack structures; and forming a plurality of S/D regions.
    Type: Application
    Filed: December 7, 2012
    Publication date: September 17, 2015
    Inventors: Qiuxia Xu, Gaobo Xu, Huajie Zhou, Huilong Zhu, Dapeng Chen
  • Patent number: 9136181
    Abstract: A method for manufacturing a semiconductor device, comprising: defining an active region on the semiconductor substrate; forming an interfacial oxide layer on a surface of the semiconductor substrate; forming a high-K gate dielectric on the interfacial oxide layer; forming a first metal gate layer on the high-K gate dielectric; forming a dummy gate layer on the first metal gate layer; patterning the dummy gate layer, the first metal gate layer, the high-K gate dielectric and the interfacial oxide layer to form a gate stack structure; forming a gate spacer surrounding the gate stack structure; forming S/D regions for NMOS and PMOS respectively; depositing interlayer dielectric and planarization by CMP to expose the surface of dummy gate layer; removing the dummy gate layer so as to form a gate opening; implanting dopant ions into the first metal gate layer; forming a second metal gate layer on the first metal gate layer so as to fill the gate opening; and performing annealing, so that the dopant ions diffuse a
    Type: Grant
    Filed: December 7, 2012
    Date of Patent: September 15, 2015
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Qiuxia Xu, Huilong Zhu, Gaobo Xu, Huajie Zhou, Dapeng Chen
  • Publication number: 20150170974
    Abstract: A method for manufacturing a semiconductor device, comprising: defining an active region on the semiconductor substrate; forming an interfacial oxide layer on a surface of the semiconductor substrate; forming a high-K gate dielectric on the interfacial oxide layer; forming a first metal gate layer on the high-K gate dielectric; forming a dummy gate layer on the first metal gate layer; patterning the dummy gate layer, the first metal gate layer, the high-K gate dielectric and the interfacial oxide layer to form a gate stack structure; forming a gate spacer surrounding the gate stack structure; forming S/D regions for NMOS and PMOS respectively; depositing interlayer dielectric and planarization by CMP to expose the surface of dummy gate layer; removing the dummy gate layer so as to form a gate opening; implanting dopant ions into the first metal gate layer; forming a second metal gate layer on the first metal gate layer so as to fill the gate opening; and performing annealing, so that the dopant ions diffuse a
    Type: Application
    Filed: December 7, 2012
    Publication date: June 18, 2015
    Inventors: Qiuxia Xu, Huilong Zhu, Gaobo Xu, Huajie Zhou, Dapeng Chen
  • Patent number: 9049061
    Abstract: This invention discloses a CMOS device, which includes: a first MOSFET; a second MOSFET different from the type of the first MOSFET; a first stressed layer covering the first MOSFET and having a first stress; and a second stressed layer covering the second MOSFET, wherein the second stressed layer is doped with ions, and thus has a second stress different from the first stress. This invention's CMOS device and method for manufacturing the same make use of a partitioned ion implantation method to realize a dual stress liner, without the need of removing the tensile stressed layer on the PMOS region or the compressive stressed layer on the NMOS region by photolithography/etching, thus simplifying the process and reducing the cost, and at the same time, preventing the stress in the liner on the NMOS region or PMOS region from the damage that might be caused by the thermal process of the deposition process.
    Type: Grant
    Filed: April 11, 2012
    Date of Patent: June 2, 2015
    Assignee: The Institute of Microelectronics Chinese Academy of Science
    Inventors: Qiuxia Xu, Chao Zhao, Gaobo Xu
  • Patent number: 9029225
    Abstract: The present disclosure discloses a method for manufacturing an N-type MOSFET, comprising: forming a part of the MOSFET on a semiconductor substrate, the part of the MOSFET comprising source/drain regions in the semiconductor substrate, a replacement gate stack between the source/drain regions above the semiconductor substrate, and a gate spacer surrounding the replacement gate stack; removing the replacement gate stack of the MOSFET to form a gate opening exposing a surface of the semiconductor substrate; forming an interface oxide layer on the exposed surface of the semiconductor; forming a high-K gate dielectric layer on the interface oxide layer in the gate opening; forming a first metal gate layer on the high-K gate dielectric layer; implanting dopant ions into the first metal gate layer; and performing annealing to cause the dopant ions to diffuse and accumulate at an upper interface between the high-K gate dielectric layer and the first metal gate layer and a lower interface between the high-K gate diel
    Type: Grant
    Filed: December 7, 2012
    Date of Patent: May 12, 2015
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Qiuxia Xu, Huilong Zhu, Huajie Zhou, Gaobo Xu
  • Publication number: 20150011069
    Abstract: A method for manufacturing a PMOSFET including defining an active region for the PMOSFET on a semiconductor substrate; forming an interfacial oxide layer on a surface of the substrate; forming a high-K gate dielectric layer on the interfacial oxide layer; forming a metal gate layer on the dielectric layer; implanting dopant ions into the metal gate layer; forming a Poly-Si layer on the metal gate layer; patterning the Poly-Si layer, the metal gate layer, the dielectric layer and the interfacial oxide layer to form a gate stack; forming a gate spacer surrounding the gate stack; and forming S/D regions. During annealing to form the S/D regions, dopant ions implanted in the metal gate layer may accumulate at upper and bottom interfaces of the dielectric, and electric dipoles with appropriate polarities are generated by interface reaction at the bottom interface, so that the metal gate has its effective work function adjusted.
    Type: Application
    Filed: December 7, 2012
    Publication date: January 8, 2015
    Inventors: Qiuxia Xu, Gaobo Xu, Huajie Zhou, Huilong Zhu, Dapeng Chen
  • Patent number: 8822292
    Abstract: The present disclosure provides a method for forming and controlling a molecular level SiO2 interface layer, mainly comprising: cleansing before growing the SiO2 interface layer, growing the molecular level ultra-thin SiO2 interface layer; and controlling reaction between high-K gate dielectric and the SiO2 interface layer to further reduce the SiO2 interface layer. The present disclosure can strictly prevent invasion of oxygen during process integration. The present disclosure can obtain a good-quality high-K dielectric film having a small EOT. The manufacturing process is simple and easy to integrate. It is also compatible with planar CMOS process, and can satisfy requirement of high-performance nanometer level CMOS metal gate/high-K device of 45 nm node and below.
    Type: Grant
    Filed: February 28, 2012
    Date of Patent: September 2, 2014
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Qiuxia Xu, Gaobo Xu
  • Patent number: 8786032
    Abstract: The present application provides a p-type semiconductor device and a method for manufacturing the same. The structure of the device comprises: a semiconductor substrate; a channel region positioned in the semiconductor substrate; a gate stack which is positioned on the channel region comprising a gate dielectric layer and a gate electrode, wherein the gate dielectric layer is positioned on the channel region and the gate electrode is positioned on the gate dielectric layer; and source/drain regions positioned at the two sides of the channel region and embedded into the semiconductor substrate; wherein the element Al is distributed in at least one of the upper surface, the bottom surface of the gate dielectric layer and the bottom surface of the gate electrode. The embodiments of the present invention are applicable for manufacturing MOSFET.
    Type: Grant
    Filed: February 27, 2011
    Date of Patent: July 22, 2014
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Gaobo Xu, Qiuxia Xu
  • Patent number: 8748250
    Abstract: The present invention provides a method for integrating the dual metal gates and the dual gate dielectrics into a CMOS device, comprising: growing an ultra-thin interfacial oxide layer or oxynitride layer by rapid thermal oxidation; forming a high-k gate dielectric layer on the ultra-thin interfacial oxide layer by physical vapor deposition; performing a rapid thermal annealing after the deposition of the high-k; depositing a metal nitride gate by physical vapor deposition; doping the metal nitride gate by ion implantation with P-type dopants for a PMOS device, and with N-type dopants for an NMOS device, with a photoresist layer as a mask; depositing a polysilicon layer and a hard mask by a low pressure CVD process, and then performing photolithography process and etching the hard mask; removing the photoresist, and then etching the polysilicon layer/the metal gate/the high-k dielectric layer sequentially to provide a metal gate stack; forming a first spacer, and performing ion implantation with a low energy
    Type: Grant
    Filed: February 21, 2011
    Date of Patent: June 10, 2014
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Qiuxia Xu, Gaobo Xu
  • Publication number: 20140154853
    Abstract: The present disclosure discloses a method for manufacturing an N-type MOSFET, comprising: forming a part of the MOSFET on a semiconductor substrate, the part of the MOSFET comprising source/drain regions in the semiconductor substrate, a replacement gate stack between the source/drain regions above the semiconductor substrate, and a gate spacer surrounding the replacement gate stack; removing the replacement gate stack of the MOSFET to form a gate opening exposing a surface of the semiconductor substrate; forming an interface oxide layer on the exposed surface of the semiconductor; forming a high-K gate dielectric layer on the interface oxide layer in the gate opening; forming a first metal gate layer on the high-K gate dielectric layer; implanting dopant ions into the first metal gate layer; and performing annealing to cause the dopant ions to diffuse and accumulate at an upper interface between the high-K gate dielectric layer and the first metal gate layer and a lower interface between the high-K gate diel
    Type: Application
    Filed: December 7, 2012
    Publication date: June 5, 2014
    Applicant: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Qiuxia Xu, Huilong Zhu, Huajie Zhou, Gaobo Xu
  • Publication number: 20130249012
    Abstract: This invention discloses a CMOS device, which includes: a first MOSFET; a second MOSFET different from the type of the first MOSFET; a first stressed layer covering the first MOSFET and having a first stress; and a second stressed layer covering the second MOSFET, wherein the second stressed layer is doped with ions, and thus has a second stress different from the first stress. This invention's CMOS device and method for manufacturing the same make use of a partitioned ion implantation method to realize a dual stress liner, without the need of removing the tensile stressed layer on the PMOS region or the compressive stressed layer on the NMOS region by photolithography/etching, thus simplifying the process and reducing the cost, and at the same time, preventing the stress in the liner on the NMOS region or PMOS region from the damage that might be caused by the thermal process of the deposition process.
    Type: Application
    Filed: April 11, 2012
    Publication date: September 26, 2013
    Inventors: Qiuxia Xu, Chao Zhao, Gaobo Xu
  • Publication number: 20130240990
    Abstract: A method for manufacturing a semiconductor structure and a semiconductor device manufactured using the same are disclosed. In replacement gate process, the present invention is capable of reducing contact resistance at source/drain regions through forming doped amorphous Si layers above source/drain regions, forming contact holes (310) penetrating through the interlayer dielectric layer (300) and amorphous Si layers (251); wherein the contact holes (310) at least expose part of the source/drain regions (110), and contact layers are formed at the exposed area of the source/drain regions and sidewalls of the contact holes in the amorphous Si layer. Since contact layers are formed after high-k dielectric layer has been annealed, metal silicide layers are protected from damages at high temperatures.
    Type: Application
    Filed: December 2, 2011
    Publication date: September 19, 2013
    Inventors: Haizhou Yin, Wei Jiang, Gaobo Xu
  • Patent number: 8530302
    Abstract: A method for manufacturing a CMOS FET comprises forming a first interfacial SiO2 layer on a semiconductor substrate after formation a conventional dielectric isolation; forming a stack a first high-K gate dielectric/a first metal gate; depositing a first hard mask; patterning the first hard mask by lithography and etching; etching the portions of the first metal gate and the first high-K gate dielectric that are not covered by the first hard mask. A second interfacial SiO2 layer and a stack of a second high-K gate dielectric/a second metal gate are then formed; a second hard mask is deposited and patterned by lithograph and etching; the portions of the second metal gate and the second high-K gate dielectric that are not covered by the second hard mask are etched to expose the first hard mask on the first metal gate.
    Type: Grant
    Filed: November 22, 2011
    Date of Patent: September 10, 2013
    Assignee: The Institute of Microelectronics, Chinese Academy of Science
    Inventors: Qiuxia Xu, Yongliang Li, Gaobo Xu
  • Publication number: 20130130448
    Abstract: The present disclosure provides a method for forming and controlling a molecular level SiO2 interface layer, mainly comprising: cleansing before growing the SiO2 interface layer, growing the molecular level ultra-thin SiO2 interface layer; and controlling reaction between high-K gate dielectric and the SiO2 interface layer to further reduce the SiO2 interface layer. The present disclosure can strictly prevent invasion of oxygen during process integration. The present disclosure can obtain a good-quality high-K dielectric film having a small EOT. The manufacturing process is simple and easy to integrate. It is also compatible with planar CMOS process, and can satisfy requirement of high-performance nanometer level CMOS metal gate/high-K device of 45 nm node and below.
    Type: Application
    Filed: February 28, 2012
    Publication date: May 23, 2013
    Inventors: Qiuxia Xu, Gaobo Xu