Abstract: An integrated device, a semiconductor device, and an integrated device manufacturing method are provided, to improve capacitor integration density of the integrated device. The integrated device includes: A first dielectric layer is disposed on a first metal layer; the first metal layer, the first dielectric layer, and a gate metal layer on the first dielectric layer form a first capacitor; the gate metal layer, a second dielectric layer on the gate metal layer, and a second metal layer on the second dielectric layer form a second capacitor; and the first metal layer is connected to the second metal layer through a first conductor structure, so that the first capacitor and the second capacitor are connected in parallel.

Abstract: A field effect transistor includes a channel layer, a source, a drain, a gate structure, and a gate metal layer; and the gate structure includes a P-type gallium nitride layer and an N-type gallium nitride layer that are disposed in a stacking manner, so that a gate metal/pGaN Schottky diode is replaced with an nGaN/pGaN reverse bias diode, to improve a gate voltage-withstand capability of the field effect transistor, thereby improving a breakdown capability of the field effect transistor. A doping density of the P-type gallium nitride layer is between 1×1018 cm?3 and 1×1019 cm?3, so that a charge storage effect during operation of a device can be reduced, carriers at the pGaN layer can be exhausted as much as possible, and redundant-charge storage is avoided, thereby improving operating threshold voltage stability of the device.

Abstract: The disclosure relates to a Gallium Nitride power transistor, comprising: a buffer layer; and a barrier layer having a top side, a bottom side, the bottom side facing the buffer layer, the bottom side of the barrier layer is placed on the buffer layer; an interlayer interposed between a p-type doped Gallium Nitride layer and a metal gate layer, the interlayer is made of a III-V compound semiconductor comprising a combination of at least one group III element with at least one group V element, the p-type doped Gallium Nitride layer is placed on the top side of the barrier layer, the metal gate layer is electrically connected to the p-type doped Gallium Nitride layer via the interlayer to form a rectifying metal-semiconductor junction with the p-type doped Gallium Nitride layer.

Abstract: This application provides a chip, a gallium nitride power device, and a power drive circuit. The chip includes a substrate and a plurality of gallium nitride components disposed on the substrate. The plurality of gallium nitride components are arranged in an array. The gallium nitride component includes an active region and a non-active region separately disposed on the substrate. The non-active region surrounds a side surface of the active region. The active region includes a heterojunction formed by a gallium nitride layer and an aluminum gallium nitride layer. The non-active region includes a plurality of grooves spaced apart. The plurality of grooves penetrate the non-active region and expose the substrate, and the plurality of grooves are used to isolate adjacent gallium nitride components.

Abstract: A gallium nitride (GaN) device, where a drain of the GaN device includes a p-type (P-GaN) layer and a drain metal. The drain metal includes a plurality of first structural intervals and a plurality of second structural intervals. The plurality of first structural intervals and the plurality of second structural intervals are alternately distributed in the gate width direction. In this way, the drain metal implements local injection of holes for the device in the first structural intervals, and forms ohmic contact in the second structural intervals, implementing current conduction from a drain to a source of the device.

Abstract: The technology described herein is generally directed towards a self-bootstrap integrated gate driver circuit with high driving speed, enhanced driving capability and rail-to-rail output. A capacitor and diode are used with a first inverter coupled to a control signal input terminal, a second inverter coupled to the first inverter, a push-pull circuit comprising a pull-up transistor and a pull-down transistor and a power device comprising a power device transistor with a gate. Control signal input at one state controls the first inverter to a first output state, turns on the pull-down transistor to discharge the gate of the power device transistor, turns off the power device and charges the capacitor through the diode. The control signal input in another state controls the first inverter to a second output state, turns off the pull-down transistor and turns on the pull-up transistor via the capacitor to turn on the power device.

Abstract: The technology described herein is generally directed towards a self-bootstrap integrated gate driver circuit with high driving speed, enhanced driving capability and rail-to-rail output. A capacitor and diode are used with a first inverter coupled to a control signal input terminal, a second inverter coupled to the first inverter, a push-pull circuit comprising a pull-up transistor and a pull-down transistor and a power device comprising a power device transistor with a gate. Control signal input at one state controls the first inverter to a first output state, turns on the pull-down transistor to discharge the gate of the power device transistor, turns off the power device and charges the capacitor through the diode. The control signal input in another state controls the first inverter to a second output state, turns off the pull-down transistor and turns on the pull-up transistor via the capacitor to turn on the power device.