Abstract: The disclosure discloses a layout design method, chip and terminal of power device, wherein the non-top metal layout design: the metal is routed along the first direction and several metal wires that fully occupy the available area of the die unit are thereby obtained, and the wiring properties of the metal wires are sequentially changed at intervals, making the source ends and the drain ends of the device are alternately distributed at intervals, and the metal routing in two or more layers of non-top metal are arranged vertically; the top metal layout design: the source end region and drain end region in the top metal are formed into sheets independently and the pad is arranged in the top metal region; eventually realize the interconnection of metal layers and complete the layout design.

Abstract: The disclosure relates to the field of power electronic technology, and discloses an electrothermal co-simulation method, system and terminal for the power electronic system, comprising the following steps: carrying out electrical simulation on the power semiconductor device and its power circuit, and junction temperature simulation on the power semiconductor device; acquiring real-time electrical parameters in the electrical simulation process; suspending the electrical simulation in a steady state until the steady state of the electrical simulation is changed; and calculating the junction temperature according to the real-time electrical parameters and in combination with the real-time loss of the power semiconductor device in the electrical simulation process. The disclosure dynamically controls the electrical simulation state, thereby reducing the calculation amount in the simulation process and achieving the purpose of accelerating the simulation convergence.