Patents by Inventor GAPKYOUNG KIM

GAPKYOUNG KIM has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240356726
    Abstract: An encryption device includes an encryption core circuit configured to generate output data by performing an encryption operation on input data, and an encryption controller circuit configured to control an operation of the encryption core. The encryption core circuit includes a shiftrow circuit configured to generate shift data by performing a shiftrow operation on the input data, a security circuit configured to generate permutation data by performing a permutation operation including a mixcolumn multiplication operation on the shift data, a mixcolumn addition circuit configured to generate first mid data by performing a mixcolumn addition operation on the permutation data, and a round key addition operation circuit configured to generate the output data by performing a round key addition operation on the first mid data.
    Type: Application
    Filed: April 12, 2024
    Publication date: October 24, 2024
    Inventors: Gapkyoung Kim, Jaehyeok Kim, Yongki Lee, Hongmook Choi
  • Publication number: 20240021261
    Abstract: A memory device includes a memory module and a BIST logic circuit. The BIST logic circuit includes; a pattern generator configured to generate first main data including a first portion, an error correction code (ECC) encoder configured to generate first parity data based on the first main data, and a parity control circuit configured to generate mask data based on the first parity data and the first main data, and generate first substituted parity data based on the mask data and the first parity data, wherein a pattern of the first substituted parity data is the same as a pattern of the first portion of the first main data.
    Type: Application
    Filed: September 27, 2023
    Publication date: January 18, 2024
    Inventors: Eunhye Oh, Jaehyeok Kim, Yong Ki Lee, Gapkyoung Kim, Taewook Park
  • Patent number: 11804276
    Abstract: A memory device includes a memory module and a BIST logic circuit. The BIST logic circuit includes; a pattern generator configured to generate first main data including a first portion, an error correction code (ECC) encoder configured to generate first parity data based on the first main data, and a parity control circuit configured to generate mask data based on the first parity data and the first main data, and generate first substituted parity data based on the mask data and the first parity data, wherein a pattern of the first substituted parity data is the same as a pattern of the first portion of the first main data.
    Type: Grant
    Filed: September 7, 2021
    Date of Patent: October 31, 2023
    Inventors: Eunhye Oh, Jaehyeok Kim, Yong Ki Lee, Gapkyoung Kim, Taewook Park
  • Publication number: 20220293205
    Abstract: A memory device includes a memory module and a BIST logic circuit. The BIST logic circuit includes; a pattern generator configured to generate first main data including a first portion, an error correction code (ECC) encoder configured to generate first parity data based on the first main data, and a parity control circuit configured to generate mask data based on the first parity data and the first main data, and generate first substituted parity data based on the mask data and the first parity data, wherein a pattern of the first substituted parity data is the same as a pattern of the first portion of the first main data.
    Type: Application
    Filed: September 7, 2021
    Publication date: September 15, 2022
    Inventors: EUNHYE OH, JAEHYEOK KIM, YONG KI LEE, GAPKYOUNG KIM, TAEWOOK PARK