Patents by Inventor Garbiel Daniel

Garbiel Daniel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5978931
    Abstract: A fault-tolerant memory device provided with a variable domain redundancy replacement (VDRR) arrangement is described. The memory device includes: a plurality of primary memory arrays; a plurality of domains having at least portions of one domain common to another domain to form an overlapped domain area, and at least one of the domains overlapping portions of at least two of the primary memory arrays; redundancy units, coupled to each of the domains, for replacing faults contained within each of the domains; control circuitry for directing at least one of the faults within one of the domains to be replaced with the redundancy units, wherein at least one other fault of the one domain is replaced by the redundancy unit coupled to another of the domains, if the at least one other fault is positioned within the overlapped domain area. Each redundancy unit supporting the primary memory arrays includes a plurality of redundant elements.
    Type: Grant
    Filed: July 16, 1997
    Date of Patent: November 2, 1999
    Assignees: International Business Machines Corporation, Siemens Aktiengesellschaft
    Inventors: Toshiaki Kirihata, Garbiel Daniel, Jean-Marc Dortu, Karl-Peter Pfefferl
  • Patent number: 5881003
    Abstract: A method of making a fault-tolerant memory device employing a variable domain redundancy replacement (VDRR) arrangement is described. The method includes the steps of: subdividing the memory into a plurality of primary memory arrays; defining a plurality of domains, at least one of the domains having at least a portion common to another domain to form an overlapped domain area, and wherein at least one of the domains overlaps portions of at least two of the primary arrays; allocating redundancy means to each of the domains to replace faults contained within each of the domains; and replacing at least one of the faults within one of the domains with the redundancy means coupled to the one domain, and at least one other fault of the one domain is replaced by the redundancy means coupled to another of the domains, if the at least one other fault is positioned within the overlapped domain area. Each redundancy unit supporting the primary memory arrays includes a plurality of redundant elements.
    Type: Grant
    Filed: July 16, 1997
    Date of Patent: March 9, 1999
    Assignees: International Business Machines Corporation, Siemens Aktiengesellschaft
    Inventors: Toshiaki Kirihata, Garbiel Daniel, Jean-Marc Dortu, Karl-Peter Pfefferl