Patents by Inventor Gardner D. Jones
Gardner D. Jones has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 5175863Abstract: The architecture operates the ALU and MACU through a register file that serves as a general buffer pool for operands. All operands transfers take place between data memory through this register file. The ALU and MACU have equal access to all data in the file. Further the file is the buffer for previous ALU results. In this manner, the bandwidths of all the individual units, data buses, ALU and MACU can be fully utilized without conflicts. In general, the proposed configuration relies on the redundancy or latency in many signal processing computations where data and results are used and reused in the overall computation and must remain in holding registers. The register file gives this capability providing these operands for use independently by both the ALU and MACU. Without a common register file, operands would have to be reloaded as the computation continues. These redundant loads reduce the throughput for the computation.Type: GrantFiled: October 23, 1989Date of Patent: December 29, 1992Assignee: International Business Machines CorporationInventor: Gardner D. Jones, Jr.
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Patent number: 4794517Abstract: This processor is a single chip implementation of an architecture that is designed to expeditiously handle certain tasks commonly associated with signal processing. Sequential multiply and accumulate operations, in particular, can be accomplished quite efficiently. The processor is pipelined in two areas. Instructions are passed through a three phase pipeline and consist of fetch, decode and execute, while the multiplier utilizes a two phase pipeline. The data flow is parallel and of 16-bit width throughout. The instruction store is maintained separately from the data store and provisions are included for having the processor enabled to read and write its own instruction store. Some parallel or compound instructions are implemented to permit transfer actions such as storage or I/O to or from instruction registers to occur concurrently with a compute action in different segments of the data flow. The arithmetic capabilities of the processor include both the separate multiplier and a full arithmetic logic unit.Type: GrantFiled: April 15, 1985Date of Patent: December 27, 1988Assignee: International Business Machines CorporationInventors: Gardner D. Jones, Larry D. Larsen, Daniel J. Esteban
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Patent number: 4712235Abstract: An improved echo canceller control method utilizes two adaptive level detectors for controlling or inhibiting the updating of coefficients in the echo canceller. Updating is permitted only when an actual received signal is present and no transmit signal as measured by the adaptive level detector exists. During periods when no transmit or receive signals are present, update is inhibited and the adaptive level detector establishes a noise reference level. When transmission activity is present but no receive activity is present, inhibiting of the echo canceller updating allows the adaptive level detector to seek and establish the background noise reference level and avoids the disruption of the echo canceller coefficients that would occur from double talk if a receive signal were suddenly to become present. When actual double talk, i.e., both receive and transmit activities are present occurs, updating is also inhibited for the same reason.Type: GrantFiled: November 19, 1984Date of Patent: December 8, 1987Assignee: International Business Machines CorporationInventor: Gardner D. Jones, Jr.
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Patent number: 4663675Abstract: An improved method and apparatus of digital speech storage and retrieval is described utilizing silence gaps for insertion of control signal information. This prevents interference with incoming control signals by feedback of signals through the hybrid circuit that occurs during playback of the stored speech. A diverter switch is controlled during the playback mode to allow incoming control signals to be decoded only when gaps of sufficient length are detected in the played back program.Type: GrantFiled: May 4, 1984Date of Patent: May 5, 1987Assignee: International Business Machines CorporationInventors: Gardner D. Jones, Jr., Larry D. Larsen
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Patent number: 4528659Abstract: The disclosed invention allows digital data to be integrated with a digital voice signal in a simple manner that does not affect the voice transmission quality. Digital data is inserted in quiet or "no speech" portions of the voice signal stream when such quiet periods are detected. No flags, headers, or other indications are necessary upon the insertion of digital data. The digital data is encoded in a two byte pattern in which the scaling bits are set high and the sign bit alternates in each eight bit byte. Four bits of each byte are thus reserved for scaling and sign purposes, but the remaining four bits are available for data transmission. Setting the three scaling bits high and alternating the sign bit has the effect of indicating to the receiver that voice is not present.Type: GrantFiled: December 17, 1981Date of Patent: July 9, 1985Assignee: International Business Machines CorporationInventor: Gardner D. Jones, Jr.
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Patent number: 4476536Abstract: A simple method and apparatus for generating approximate sine waves is described. A digital accumulator or adder is driven at a basic counting rate to accumulate increments representative of phase with the total sum representative of total phase angle of a sine wave. The output is periodically sampled and the value is converted into an analog output voltage in a normal D to A converter. A straight line ramp voltage approximation to the sine wave function is created as the result. The accumulator operates in this fashion until a total phase angle of approximately 45.degree. is accumulated. Then accumulation value additions are then accorded 1/2 their usual significance until 671/2.degree. of total phase angle are accumulated. Then accumulation is then at 1/4 the basic significance accorded to increments until 90.degree. is reached. The symmetry of the sine wave allows the 0.degree. through 90.degree. samples to be used to generate the full 360.degree.Type: GrantFiled: December 17, 1981Date of Patent: October 9, 1984Assignee: International Business Machines CorporationInventor: Gardner D. Jones, Jr.
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Patent number: 4455649Abstract: The improved multiplexer described herein uses split band encoding across a plurality of input ports to increase the statistical advantage for compression gains but does not require a large number of input ports to achieve its advantage.Type: GrantFiled: January 15, 1982Date of Patent: June 19, 1984Assignee: International Business Machines CorporationInventors: Daniel J. Esteban, Gardner D. Jones, Jr., Lee S. Rogers
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Patent number: 4003001Abstract: A frequency shift keyed (FSK) modulator capable of substantially simultaneously modulating a plurality of binary encoded data signals at different baud rates and modulation frequencies for substantially simultaneous transmission over a plurality of communication lines and in which the modulated signals are of narrow bandwidth thus requiring the same simple RC filter for all lines regardless of the baud rates or signalling frequencies used.Type: GrantFiled: November 10, 1975Date of Patent: January 11, 1977Assignee: International Business Machines CorporationInventor: Gardner D. Jones, Jr.
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Patent number: 3987374Abstract: A multi-line multi-mode modulator uses compatible digital modulation techniques for multifrequency (MF), frequency shift keyed (FSK) and differential phase shift keyed (DPSK) modulation to achieve a multi-line multi-mode modulator which is capable of handling a plurality of lines requiring a dynamic mix of the three modulation techniques. The compatible modulation techniques utilize bandwidth reduction schemes which enable the use of simple RC filters on each output line for the sole purpose of removing the quantizing noise introduced by the digital modulation technique.Type: GrantFiled: November 10, 1975Date of Patent: October 19, 1976Assignee: International Business Machines CorporationInventor: Gardner D. Jones, Jr.
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Patent number: 3983381Abstract: A digital automatic gain control circuit in which the input signal is multiplied by a gain control parameter whose value is generated in a feedback loop such that the resultant product has specified constant metric.Type: GrantFiled: December 18, 1974Date of Patent: September 28, 1976Assignee: International Business Machines CorporationInventor: Gardner D. Jones, Jr.
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Patent number: 3958191Abstract: A multi-line multi-mode modulator uses compatible digital modulation techniques for multifrequency (MF), frequency shift keyed (FSK) and differential phase shift keyed (DPSK) modulation to achieve a multi-line multi-mode modulator which is capable of handling a plurality of lines requiring a dynamic mix of the three modulation techniques. The compatible modulation techniques utilize bandwidth reduction schemes which enable the use of simple RC filters on each output line for the sole purpose of removing the quantizing noise introduced by the digital modulation technique.Type: GrantFiled: November 21, 1974Date of Patent: May 18, 1976Assignee: International Business Machines CorporationInventor: Gardner D. Jones, Jr.