Abstract: A FIFO store for data packets and their respective status words includes space for the writing of a predetermined sync word or one of a cyclic sequence of predetermined sync words with each status word. The sync word can be used to prevent forwarding of a packet and as an aid to fault diagnosis if on reading the status word the sync word does not match any of the predetermined sync words.

Abstract: A network device incorporating selective compression of stored data packets is disclosed. The network device receives, stores and forwards data packets and includes a system for applying a compression algorithm to packets after their header portions and storing the partially compressed packets, which are decompressed after readout from storage and before they are forwarded. Lengths of a packet as received and as subject to the compression algorithm are compared to prevent storage when the algorithm fails to produce a shorter packet.

Abstract: A network switch includes a plurality of receive ports for receiving addressed data packets and a plurality of transmit ports for forwarding the addressed data packets and structure responsive to data in said the packets for directing received packets to the transmit ports. In respect of at least one of the transmit ports the switch includes an output buffer for storing data packets before they are forwarded from the port and an allocation controller. The allocation controller allocates each packet destined for the buffer and each packet leaving the buffer for the port into at least one of a plurality of categories, which may be based on priority or protocol data and may define traffic types such as video or audio.

Abstract: A network switch includes a plurality of receive ports for receiving addressed data packets and a plurality of transmit ports for forwarding the addressed data packets and is responsive to data in the packets for directing received packets to the transmit ports. The switch includes, with respect to at least one transmit port, a bandwidth controller for at least one selected packet type. The bandwidth controller diminishes an aggregate count in response to the sizes of packets of the one type destined for the transmit port and continually augments the aggregate count at a selectable rate. The switch compares the aggregate count with a threshold and initiates a discard of packets of the one type before they can be forwarded from the transmit port so as to limit the proportion of available bandwidth occupied by packet so of the one type with respect to the transmit port.

Abstract: An application specific integrated circuit includes a multiplicity of operational blocks each of which includes at least one respective data bus and at least one respective visibility bus and a respective addressable multiplexer for selecting between those buses to provide an output on a to respective block bus. An interface block includes a first addressable multiplexer for selecting output data from a selected one of the blocks and providing an output; a register coupled to the output of the first addressable multiplexer; and a second addressable multiplexer for selecting between data provided by the output of the first addressable multiplexer and data in the register. Different portions of externally supplied address words are applied to the first addressable multiplexer and the respective addressable multiplexer, and a decoder is responsive to the address words for controlling the second addressable multiplexer. The arrangement provides a common multiplexing system for data buses and visibility buses.

Abstract: A system including an ordered data table containing linked lists of MAC addresses has a multiplicity of search engines which have their access to an LRU engine under the control of a token which is passed from one search engine to the next when the LRU engine has completed reordering the table after an address look-up. The system avoids conflicts between searching and reordering and allows reordering to be performed at a controlled rate.

Abstract: A network switch includes a transmit queue of packets along with indication (e.g. in respective status words) of the type of each packet and its size. An arbitrator includes a counter which is incremented by the size (e.g. in bytes) of each packet of a first type (e.g. ‘low-loss’) and decremented by a scaled size of each packet of a second type (e.g. ‘normal loss’). If the queue exceeds a set limit, preferably less than the maximum possible size of the queue, packets are discarded if a scaled packet of the second type exceeds the net content of the counter.

Abstract: A network device which includes flow control, being responsive to a control frame prescribing a pause in the forwarding of packet from a port, sorts received packets intended for forwarding from that port into a first queue, e.g. critical latency traffic and at least one other queue. A count of the number of packets in the first queue is determined at the onset of a pause and at least that number of packets are discarded from the first queue if the pause time exceeds a programmable reference.

Abstract: A FIFO store for data packets and their respective status words includes space for the writing of a predetermined sync word or one of a cyclic sequence of predetermined sync words with each status word. The sync word can be used to prevent forwarding of a packet and as an aid to fault diagnosis if on reading the status word the sync word does not match any of the predetermined sync words.

Abstract: A plurality of circuit cards include at least a first card having a first internal power rail, an earth connection, respective operating circuits powered from the first power rail, external terminals coupled to its operating circuit, and a first external connection. A second of the plural cards has a second internal power rail, an earth connection, respective operating circuits powered from the second power rail, external terminals coupled to its operating circuit, and a second external connector. The first card includes a bipolar transistor with an emitter-base junction forwardly biased in response to normal voltage between the first power rail and the earth connection and a collector connected to the first external connector. The second card includes a resistive connection between its second internal power rail and the second external connector and circuits responsive to changes in voltage level at the second connector.