Patents by Inventor Gareth J. Nicholls
Gareth J. Nicholls has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8027416Abstract: A machine-readable medium thereupon stored a design structure; the design structure includes a receiver for a data communications system. The receiver includes a data path for receiving a data signal from a data channel, the data path comprising an automatic gain control (AGC) loop; and, a signal detector for generating a data valid signal indicative of the validity of the data signal in response to detection of the data signal on the channel exceeding a threshold and in dependence upon gain information from the AGC loop in the data path.Type: GrantFiled: March 6, 2008Date of Patent: September 27, 2011Assignee: International Business Machines CorporationInventors: James S. Mason, Louis C. Hsu, Phil J. Murfet, Gareth J. Nicholls
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Patent number: 8027415Abstract: A receiver for a data communications system comprises: a data path for receiving a data signal from a data channel, the data path comprising an automatic gain control (AGC) loop; and, a signal detector for generating a data valid signal indicative of the validity of the data signal in response to detection of the data signal on the channel exceeding a threshold and in dependence upon gain information from the AGC loop in the data path.Type: GrantFiled: April 19, 2007Date of Patent: September 27, 2011Assignee: International Business Machines CorporationInventors: James S. Mason, Louis C. Hsu, Phil J. Murfet, Gareth J. Nicholls
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Patent number: 7809054Abstract: Disclosed are a receiver circuit, method and design architecture of a decision feedback equalizer (DFE) Clock-And-Data Recovery (CDR) architecture that utilizes/produces one sample-per-bit in the receiver and reduces bit-error-rate (BER). An integrating receiver is combined with a decision feedback equalizer along with the appropriate (CDR) loop phase detector to maintain a single sample per bit requirement. The incoming voltage is converted to a current and connected to a current summing node. Weighted currents determined by the values of previously detected bits and their respective feedback coefficients are also connected to this node. Additionally, the summed currents is integrated and converted to a voltage. A sampler is utilized to make a bit decision based on the resulting voltage. After sampling, the integrator is reset before analysis of the next bit. The necessary amplification is achieved by maximizing the sensitivity of the latch, using integration in front of the data latch.Type: GrantFiled: April 18, 2006Date of Patent: October 5, 2010Assignee: International Business Machines CorporationInventors: Juan A. Carballo, Hayden C. Cranford, Jr., Gareth J. Nicholls, Vernon R. Norman, Martin L. Schmatz
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Publication number: 20080284517Abstract: A method of varying the gain of an amplifier and an amplifier array are provided. The amplifier array includes two or more amplifier stages (201, 202) connected in parallel with each amplifier stage having a gain control means. Input signal means (203, 204) are provided for each amplifier stage with the input signals of the amplifier stages being of different amplitude. Means for enabling and disabling an amplifier stage (216) are provided and means for summing the outputs of the enabled amplifier stages obtain an output signal (212).Type: ApplicationFiled: May 30, 2008Publication date: November 20, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Thomas J. Bardsley, Matthew R. Cordrey-Gale, James S. Mason, Philip J. Murfet, Gareth J. Nicholls
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Publication number: 20080240224Abstract: A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design of a decision feedback equalizer (DFE) Clock-And-Data Recovery (CDR) architecture that utilizes/produces one sample-per-bit in the receiver and reduces bit-error-rate (BER) is provided. The design generally includes a receiver circuit. The receiver circuit generally includes a decision feedback equalizer (DFE) that produces one sample per bit, and means for automatically self-adjusting the DFE to enable an eye centering process by which peak energy is maintained within the receiver circuit when phase error is a minimum.Type: ApplicationFiled: June 12, 2008Publication date: October 2, 2008Inventors: JUAN A. CARBALLO, Hayden C. Cranford, Gareth J. Nicholls, Vernon R. Norman, Martin L. Schmatz
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Patent number: 7397302Abstract: A method of varying the gain of an amplifier and an amplifier array are provided. The amplifier array includes two or more amplifier stages (201, 202) connected in parallel with each amplifier stage having a gain control means. Input signal means (203, 204) are provided for each amplifier stage with the input signals of the amplifier stages being of different amplitude. Means for enabling and disabling an amplifier stage (216) are provided and means for summing the outputs of the enabled amplifier stages obtain an output signal (212).Type: GrantFiled: April 13, 2007Date of Patent: July 8, 2008Assignee: International Business Machines CorporationInventors: Thomas J. Bardsley, Matthew R. Cordrey-Gale, James S. Mason, Philip J. Murfet, Gareth J. Nicholls
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Publication number: 20080146181Abstract: A machine-readable medium thereupon stored a design structure; the design structure includes a receiver for a data communications system. The receiver includes a data path for receiving a data signal from a data channel, the data path comprising an automatic gain control (AGC) loop; and, a signal detector for generating a data valid signal indicative of the validity of the data signal in response to detection of the data signal on the channel exceeding a threshold and in dependence upon gain information from the AGC loop in the data path.Type: ApplicationFiled: March 6, 2008Publication date: June 19, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: James Mason, Louis Hsu, Phil J. Murfet, Gareth J. Nicholls
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Publication number: 20080037690Abstract: A receiver for a data communications system comprises: a data path for receiving a data signal from a data channel, the data path comprising an automatic gain control (AGC) loop; and, a signal detector for generating a data valid signal indicative of the validity of the data signal in response to detection of the data signal on the channel exceeding a threshold and in dependence upon gain information from the AGC loop in the data path.Type: ApplicationFiled: April 19, 2007Publication date: February 14, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: James S. Mason, Louis C. Hsu, Phil J. Murfet, Gareth J. Nicholls
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Patent number: 7250814Abstract: A method of varying the gain of an amplifier and an amplifier array are provided. The amplifier array includes two or more amplifier stages (201, 202) connected in parallel with each amplifier stage having a gain control means. Input signal means (203, 204) are provided for each amplifier stage with the input signals of the amplifier stages being of different amplitude. Means for enabling and disabling an amplifier stage (216) are provided and means for summing the outputs of the enabled amplifier stages obtain an output signal (212).Type: GrantFiled: April 1, 2005Date of Patent: July 31, 2007Assignee: International Business Machines CorporationInventors: Thomas J. Bardsley, Matthew R. Cordrey-Gale, James S. Mason, Philip J. Murfet, Gareth J. Nicholls
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Patent number: 7085970Abstract: A method, in an oversampling clock and data recovery system, for detecting that sampling is stuck taking place at a data edge, by detecting a data edge in an early or a late region relative to a good region and incrementing a stuck early or stuck late counter; and if one counter reaching a maximum, setting a condition indicating that sampling is stuck taking place at a data edge. If a data edge is detected in the good region, or in each of an early and a late region in a single data period, the stuck counters are reset to zero. The detection of which stuck counter has reached a maximum can cause the moving of a sampling clock forward or backward, ending when a data edge occurs in a good region, or in each of an early region and a late region in a single data period.Type: GrantFiled: July 23, 2002Date of Patent: August 1, 2006Assignee: International Business Machines CorporationInventors: Gareth J. Nicholls, Alexander H. Ainscow, Jon D. Garlett, Bobak Modaress-Razavi, Vernon R. Norman, Martin L. Schmatz
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Publication number: 20040019837Abstract: A method, in an oversampling clock and data recovery system, for detecting that sampling is stuck taking place at a data edge, by detecting a data edge in an early or a late region relative to a good region and incrementing a stuck early or stuck late counter; and if one counter reaching a maximum, setting a condition indicating that sampling is stuck taking place at a data edge. If a data edge is detected in the good region, or in each of an early and a late region in a single data period, the stuck counters are reset to zero. The detection of which stuck counter has reached a maximum can cause the moving of a sampling clock forward or backward, ending when a data edge occurs in a good region, or in each of an early region and a late region in a single data period.Type: ApplicationFiled: July 23, 2002Publication date: January 29, 2004Applicant: International Business Machines CorporationInventors: Gareth J. Nicholls, Alexander H. Ainscow, Jon D. Garlett, Bobak Modaress-Razavi, Vernon R. Norman, Martin L. Schmatz