Abstract: A method and system for a frequency shift key demodulation is provided. The system includes a counting block for counting a reference clock within a window defined by a modulated signal, a detector for comparing a count value output from the counting block with digital multi-level thresholds and outputting baseband data based on the comparison, and a configurations block for configuring at least one of the counting block and the detector. The method includes counting a reference clock within a window defined by the FSK modulated signal and outputting a count value as a result of the counting, and comparing the count value with multi-level thresholds to output baseband data based on the comparison.

Abstract: A method, system and digital modulator for modulation are provided The modulator includes a dividing mechanism for dividing a reference clock by a divide value to produce a modulated signal associated with at least one input data, and a control unit for providing at least one divide sequence to the dividing mechanism. The at least one divide sequence includes a sequence of one or more divide values. The divide value of the divide sequence is configurable and selectively provided to the dividing mechanism based on the at least one input data. The method includes configuring at least one divide sequence including a sequence of one or more divide values, and selecting a divide value from the at least one divide sequence based on at least one input data. The method includes dividing a reference clock by the selected divide value and generating a modulated signal based on the divide operation.

Abstract: A method, system and digital modulator for modulation are provided The modulator includes a dividing mechanism for dividing a reference clock by a divide value to produce a modulated signal associated with at least one input data, and a control unit for providing at least one divide sequence to the dividing mechanism. The at least one divide sequence includes a sequence of one or more divide values. The divide value of the divide sequence is configurable and selectively provided to the dividing mechanism based on the at least one input data. The method includes configuring at least one divide sequence including a sequence of one or more divide values, and selecting a divide value from the at least one divide sequence based on at least one input data. The method includes dividing a reference clock by the selected divide value and generating a modulated signal based on the divide operation.

Abstract: A method and system for a frequency shift key demodulation is provided. The system includes a counting block for counting a reference clock within a window defined by a modulated signal, a detector for comparing a count value output from the counting block with digital multi-level thresholds and outputting baseband data based on the comparison, and a configurations block for configuring at least one of the counting block and the detector. The method includes counting a reference clock within a window defined by the FSK modulated signal and outputting a count value as a result of the counting, and comparing the count value with multi-level thresholds to output baseband data based on the comparison.

Abstract: A sensor includes control circuitry and a pixel having a photo site, a first storage node and a second storage node. The control circuitry operates to transfer a first collected signal produced by light from a first image from the photo site to the first storage node during a first period, to transfer a second collected signal produced by light from a second image from the photo site to the second storage node during a second period that follows the first period and to transfer the first and second collected signals out of the pixel during a third period that follows the second period. The first storage node includes a first capacitor and a first reset gate coupled directly between the first capacitor and a reset voltage. The second storage node includes a second capacitor and a second reset gate coupled directly between the second capacitor and the reset voltage.

Abstract: A sensor includes control circuitry and a pixel. The pixel includes a photo site, a first storage node and a second storage node. The control circuitry causes the pixel to transfer a first collected signal from the photo site to the first storage node during a first period, to transfer a second collected signal from the photo site to the second storage node during a second period that follows the first period, and to transfer the first and second collected signals out of the pixel during a third period that follows the second period.

Abstract: A component package includes a case with a bond shelf and a conductive layer formed on the bond shelf. The bond shelf is characterized by an inward edge and an outward edge and at least one reticulation, each reticulation being characterized by an outward edge and an inward edge. The reticulation inward edge is co-linear with the bond shelf inward edge. The conductive layer includes a mounting pad for each reticulation and a serpentine conductor connecting the mounting pads, the mounting pad being disposed between the inward edge of the reticulation and the outward edge of the reticulation. The component package further includes a chip transistor mounted on a first mounting pad and a chip resistor mounted in a first reticulation. A semiconductor circuit mounted in the component package includes a bonding pad connected to a pad on the chip transistor and one end of the chip resistor.

Abstract: A control structure for stage selection in a CCD sensor includes a well formed in a substrate and a channel formed in the well, the channel defining a channel direction. A bus structure is disposed over the channel and oriented transversely to the channel direction, the bus structure including a plurality of uniformly spaced register element sets. The plurality of uniformly spaced register element sets includes a first register element set and a plurality of remaining register element sets. The first register element set includes a first clock signal conductor and at least one other clock signal conductor. Each set of the plurality of remaining register element sets includes a first clock signal conductor and at least one other clock signal conductor.