Abstract: A synchronizing circuit for synchronizing an asynchronous serial two level input signal to a first clock signal employs a majority decoder which receives the asynchronous input signal at one of its inputs. A first latch is enabled by a second phase shifted clock signal to latch the asynchronous input signal to provide a second input to the decoder. A second latch is enabled by the first clock signal to latch the majority decoder output as the synchronized output signal. An inverted version of the output signal is fed back to the third input of the majority decoder after being delayed by an interval of less than the period of said clock signals.