Abstract: A glitch detector includes a metastability detector circuit, a reference storage circuit, and a pattern comparison circuit. The metastability detector circuit is configured to generate state signals at each cycle of the clock signal. The reference storage circuit is configured to store a logic state of each state signal based on a delayed version of the clock signal, and generate reference signals. A logic state of each reference signal is equal to a logic state of a corresponding state signal generated during a previous cycle of the clock signal. The pattern comparison circuit is configured to receive the state signals generated during a current cycle of the clock signal, the reference signals, and first and second values, and generate clock and voltage glitch signals based on first and second patterns that are associated with the state signals generated during the current cycle and the reference signals, respectively.

Abstract: A system-on-chip (SoC) is disclosed. The SoC includes a fault controlling circuit and processing circuits. The fault controlling circuit is configured to receive fault events generated by fault sources of the SoC and categorize the fault events based on a priority associated with each fault event. The fault controlling circuit is further configured to identify corresponding fault reactions for the categorized fault events and generate a set of recovery signals based on the identified fault reactions. The processing circuits are configured to receive the fault events, and further configured to receive the set of recovery signals to recover from the fault events. The fault controlling circuit thus acts as a central control system for controlling faults in the SoC.

Abstract: A glitch detector includes a metastability detector circuit, a reference storage circuit, and a pattern comparison circuit. The metastability detector circuit is configured to generate state signals at each cycle of the clock signal. The reference storage circuit is configured to store a logic state of each state signal based on a delayed version of the clock signal, and generate reference signals. A logic state of each reference signal is equal to a logic state of a corresponding state signal generated during a previous cycle of the clock signal. The pattern comparison circuit is configured to receive the state signals generated during a current cycle of the clock signal, the reference signals, and first and second values, and generate clock and voltage glitch signals based on first and second patterns that are associated with the state signals generated during the current cycle and the reference signals, respectively.

Abstract: A glitch detector includes a metastability detector circuit, a reference storage circuit, and a pattern comparison circuit. The metastability detector circuit is configured to generate state signals at each cycle of the clock signal. The reference storage circuit is configured to store a logic state of each state signal based on a delayed version of the clock signal, and generate reference signals. A logic state of each reference signal is equal to a logic state of a corresponding state signal generated during a previous cycle of the clock signal. The pattern comparison circuit is configured to receive the state signals generated during a current cycle of the clock signal, the reference signals, and first and second values, and generate clock and voltage glitch signals based on first and second patterns that are associated with the state signals generated during the current cycle and the reference signals, respectively.

Abstract: A system-on-chip (SoC) includes multiple critical components and a testing system to test the critical components. The critical components include an intellectual property (IP) core and an associated logic circuit. The testing system includes a controller, a fault injector, and a masking circuit. The controller is configured to receive a test initiation request and generate first and second select instructions. The fault injector is configured to generate and inject a set of fault inputs in the logic circuit based on the first select instruction to test the associated logic circuit and the IP core. The IP core is configured to generate a set of responses that is associated with the testing of the logic circuit and the associated IP core. The masking circuit is configured to mask and output the set of responses when the second select instruction indicates a first value and a second value, respectively.

Abstract: A glitch detector includes a metastability detector circuit, a reference storage circuit, and a pattern comparison circuit. The metastability detector circuit is configured to generate state signals at each cycle of the clock signal. The reference storage circuit is configured to store a logic state of each state signal based on a delayed version of the clock signal, and generate reference signals. A logic state of each reference signal is equal to a logic state of a corresponding state signal generated during a previous cycle of the clock signal. The pattern comparison circuit is configured to receive the state signals generated during a current cycle of the clock signal, the reference signals, and first and second values, and generate clock and voltage glitch signals based on first and second patterns that are associated with the state signals generated during the current cycle and the reference signals, respectively.

Abstract: A system-on-chip (SoC) is disclosed. The SoC includes a fault controlling circuit and processing circuits. The fault controlling circuit is configured to receive fault events generated by fault sources of the SoC and categorize the fault events based on a priority associated with each fault event. The fault controlling circuit is further configured to identify corresponding fault reactions for the categorized fault events and generate a set of recovery signals based on the identified fault reactions. The processing circuits are configured to receive the fault events, and further configured to receive the set of recovery signals to recover from the fault events. The fault controlling circuit thus acts as a central control system for controlling faults in the SoC.

Abstract: A system-on-chip (SoC) includes multiple critical components and a testing system to test the critical components. The critical components include an intellectual property (IP) core and an associated logic circuit. The testing system includes a controller, a fault injector, and a masking circuit. The controller is configured to receive a test initiation request and generate first and second select instructions. The fault injector is configured to generate and inject a set of fault inputs in the logic circuit based on the first select instruction to test the associated logic circuit and the IP core. The IP core is configured to generate a set of responses that is associated with the testing of the logic circuit and the associated IP core. The masking circuit is configured to mask and output the set of responses when the second select instruction indicates a first value and a second value, respectively.

Abstract: A system-on-chip (SoC) includes a processor, a built-in self-testing (BIST) circuitry, and an adaptive masking circuitry. The processor generates a sweep enable (SWEN) signal to initiate a self-testing operation of the SoC. The BIST circuitry receives the SWEN signal and generates a set of sweep events, such that a transition of the processor from a low power (LP) mode to an active mode is initiated based on the generation of each sweep event. The BIST circuitry further receives a status signal, and identifies a subset of sweep events at which the transition of the processor from the LP mode to the active mode failed, for generating sweep failure data. The adaptive masking circuitry receives the sweep failure data and generates a mask signal, to prevent a transition of the first processor from the LP mode to the active mode, during a non-testing operation of the SoC.

Abstract: A system-on-chip (SoC) includes a processor, a built-in self-testing (BIST) circuitry, and an adaptive masking circuitry. The processor generates a sweep enable (SWEN) signal to initiate a self-testing operation of the SoC. The BIST circuitry receives the SWEN signal and generates a set of sweep events, such that a transition of the processor from a low power (LP) mode to an active mode is initiated based on the generation of each sweep event. The BIST circuitry further receives a status signal, and identifies a subset of sweep events at which the transition of the processor from the LP mode to the active mode failed, for generating sweep failure data. The adaptive masking circuitry receives the sweep failure data and generates a mask signal, to prevent a transition of the first processor from the LP mode to the active mode, during a non-testing operation of the SoC.

Abstract: A method for managing a reset process in a processing system is provided. The method includes enabling a watch dog unit based on a power-on reset (POR) event. A stuck in reset condition indication is received at the watch dog unit and used to determine whether the received reset condition indication corresponds to an unintentional reset condition. If the received reset condition indication is an indication of an unintentional reset condition, a watch dog POR trigger signal is generated and a reset state machine is repeated for system recovery.

Abstract: In an embodiment, an electronic device includes an integrated circuit (IC) having a plurality of power domains, a first regulator coupled to a given power domain, a second regulator coupled to the given power domain, and a switching circuit coupled between the first and second regulators and configured to control an amount of current drawn by the power domain from the first and/or second regulators. In another embodiment, a method includes controlling an impedance of a switching circuit to change an amount of current, the switching circuit coupled to a given power domain of an IC configured to operate in a first mode followed by a second mode, where the switching circuit is coupled to a first regulator configured to provide more power to the IC than a second regulator, and a transition period includes turning off the first regulator and turning on the second regulator.

Abstract: An on-board reset circuit for a system-on-chip (SOC) addresses the problem of meta-stability in flip-flops on asynchronous reset that arises when different power domains or reset domains receive resets from different sources. To ameliorate the problem, a reset signal is asserted and de-asserted while the clocks are gated. The clocks are re-instated for a minimum period of time following assertion (or de-assertion) so that logic having synchronous reset can also receive the reset.

Abstract: An integrated circuit (IC) operable in functional and debug modes includes a debug enable circuit, a pad control register, a debug circuit, a pad configuration register, and an input/output (IO) pad. The debug circuit receives a functional signal from a circuit monitoring circuit, a reference signal, a debug control signal from the debug enable circuit, and pull-enable control and pull-type select control signals from the pad control register, and generates pull-enable and pull-type select signals. The pad configuration register receives the pull-enable and pull-type select signals and configures the IO pad in one of logic low, logic high, and high impedance states. When the IO pad is in either of the logic high and low states longer than a predetermined time period, then the IO pad indicates that the IC is held in a reset phase of a reset sequence.

Abstract: A microcontroller operable in a high power mode and a low power unit (LPU) run mode includes primary and LPU domains, primary and LPU mode controllers, and primary and LPU clock generator modules. The primary domain includes a first set of circuits and a first set of cores. The LPU domain includes second and third sets of circuits, a second set of cores, and a switching module. In the high power mode, the switching module connects the first and second sets of cores to at least one of the first, second and third sets of circuits, while in the LPU run mode, the switching module isolates the LPU domain from the primary domain and activates a small microcontroller system (SMS) that includes the LPU domain, the LPU mode controller and the LPU clock generator module. The SMS has further low power modes within the LPU run mode.

Abstract: An integrated circuit (IC) operable in functional and debug modes includes a debug enable circuit, a pad control register, a debug circuit, a pad configuration register, and an input/output (IO) pad. The debug circuit receives a functional signal from a circuit monitoring circuit, a reference signal, a debug control signal from the debug enable circuit, and pull-enable control and pull-type select control signals from the pad control register, and generates pull-enable and pull-type select signals. The pad configuration register receives the pull-enable and pull-type select signals and configures the IO pad in one of logic low, logic high, and high impedance states. When the IO pad is in either of the logic high and low states longer than a predetermined time period, then the IO pad indicates that the IC is held in a reset phase of a reset sequence.

Abstract: An on-board reset circuit for a system-on-chip (SOC) addresses the problem of meta-stability in flip-flops on asynchronous reset that arises when different power domains or reset domains receive resets from different sources. To ameliorate the problem, a reset signal is asserted and de-asserted while the clocks are gated. The clocks are re-instated for a minimum period of time following assertion (or de-assertion) so that logic having synchronous reset can also receive the reset.

Abstract: An integrated circuit (IC) that operates in high and low power modes includes high and low power regulators, first and second sets of circuits, a switch connecting the high power regulator and the second set of circuits, and a wake-up control system. The wake-up control system includes a state machine that enables the high power regulator when the IC is in the high power mode, and enables the low power regulator when the IC is in the low power mode. The switch is closed when the high power regulator reaches a first threshold voltage. The state machine operates on a low frequency clock signal when the IC is in the low power mode and during wake-up, and on a high frequency clock signal in the high power mode after the switch is closed.

Abstract: A microcontroller operable in a high power mode and a low power unit (LPU) run mode includes primary and LPU domains, primary and LPU mode controllers, and primary and LPU clock generator modules. The primary domain includes a first set of circuits and a first set of cores. The LPU domain includes second and third sets of circuits, a second set of cores, and a switching module. In the high power mode, the switching module connects the first and second sets of cores to at least one of the first, second and third sets of circuits, while in the LPU run mode, the switching module isolates the LPU domain from the primary domain and activates a small microcontroller system (SMS) that includes the LPU domain, the LPU mode controller and the LPU clock generator module. The SMS has further low power modes within the LPU run mode.

Abstract: A fractional frequency divider counts pulses of a digital input clock signal and enables a clock gating module when a preset count is reached. The clock gating module combines the outputs of two clock gating cells that receive, respectively, the input clock signal and an inverted version of the input clock signal. Output pulses are produced on both positive and negative edges of the input clock signal. This permits generation of output clock pulses that can be set to have a spacing and width granularity of half an input clock period, giving the advantages of low jitter and fine duty cycle control.