Patents by Inventor Garnik Taheri

Garnik Taheri has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Single IC packaging solution for multi chip modules
    Patent number: 7180171
    Abstract: A multilayer printed circuit board (PCB) interface includes a top PCB layer, a middle PCB layer, and a bottom PCB layer. A top surface of the top PCB layer receives at least one top module. The middle PCB layer includes an electrically conductive layer disposed between two dielectric layers. The electrically conductive layer forms a plurality of connectors protruding horizontally from the sides of the multilayer PCB to couple the PCB interface to a main board. A bottom surface of the bottom PCB layer receives at least one bottom module.
    Type: Grant
    Filed: January 8, 2004
    Date of Patent: February 20, 2007
    Assignee: Smart Modular Technologies, Inc.
    Inventor: Garnik Taheri