Patents by Inventor Garo Jacques DERDERIAN
Garo Jacques DERDERIAN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10832967Abstract: Device structures and fabrication methods for a field-effect transistor. A semiconductor fin includes a first section and a second section in a lengthwise arrangement, a first gate structure overlapping the first section of the semiconductor fin, and a second gate structure overlapping the second section of the semiconductor fin. A pillar is arranged in the first section of the semiconductor fin. The pillar extends through a height of the semiconductor fin and across a width of the semiconductor fin.Type: GrantFiled: August 13, 2018Date of Patent: November 10, 2020Assignee: GLOBALFOUNDRIES INC.Inventors: Hui Zang, Ruilong Xie, Garo Jacques Derderian
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Patent number: 10586736Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a hybrid fin cut with improved fin profiles and methods of manufacture. The structure includes: a plurality of fin structures in a first region of a first density of fin structures; a plurality of fin structures in a second region of a second density of fin structures; and a plurality of fin structures in a third region of a third density of fin structures. The first density, second density and third density of fin structures are different densities of fin structures, and the plurality of fin structures in the first region, the second region and the third region have a substantially uniform profile.Type: GrantFiled: June 11, 2018Date of Patent: March 10, 2020Assignee: GLOBALFOUNDRIES INC.Inventors: Haiting Wang, Ruilong Xie, Shesh Mani Pandey, Hui Zang, Garo Jacques Derderian, Scott Beasor
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Publication number: 20200051868Abstract: Device structures and fabrication methods for a field-effect transistor. A semiconductor fin includes a first section and a second section in a lengthwise arrangement, a first gate structure overlapping the first section of the semiconductor fin, and a second gate structure overlapping the second section of the semiconductor fin. A pillar is arranged in the first section of the semiconductor fin. The pillar extends through a height of the semiconductor fin and across a width of the semiconductor fin.Type: ApplicationFiled: August 13, 2018Publication date: February 13, 2020Inventors: Hui Zang, Ruilong Xie, Garo Jacques Derderian
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Publication number: 20190378763Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a hybrid fin cut with improved fin profiles and methods of manufacture. The structure includes: a plurality of fin structures in a first region of a first density of fin structures; a plurality of fin structures in a second region of a second density of fin structures; and a plurality of fin structures in a third region of a third density of fin structures. The first density, second density and third density of fin structures are different densities of fin structures, and the plurality of fin structures in the first region, the second region and the third region have a substantially uniform profile.Type: ApplicationFiled: June 11, 2018Publication date: December 12, 2019Inventors: Haiting WANG, Ruilong XIE, Shesh Mani PANDEY, Hui ZANG, Garo Jacques DERDERIAN, Scott BEASOR
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Publication number: 20190371796Abstract: First and second fin-type field effect transistors (finFETs) are formed laterally adjacent one another extending from a top surface of an isolation layer. The first finFET has a first fin structure and the second finFET has a second fin structure. An insulator layer is on the first fin structure and the second fin structure. A gate conductor intersects the first fin structure and the second fin structure, and at least the insulator layer separates the gate conductor from the first fin structure and the second fin structure. Source and drain structures are on the first fin structure and the second fin structure laterally adjacent the gate conductor. The first fin structure has sidewalls that include a step and the second fin structure has sidewalls that do not include the step. The step is approximately parallel to the surface of the isolation layer.Type: ApplicationFiled: May 31, 2018Publication date: December 5, 2019Applicant: GLOBALFOUNDRIES INC.Inventors: Hui Zang, Garo Jacques Derderian, Laertis Economikos, Chun Yu Wong, Jiehui Shu, Shesh Mani Pandey
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Publication number: 20190355615Abstract: At least one method, apparatus and system providing semiconductor devices with relatively short gate heights but without a relatively high risk of contact-to-gate shorts. In embodiments, the method, apparatus, and system may provide contact formation by way of self-aligned contact processes.Type: ApplicationFiled: July 30, 2019Publication date: November 21, 2019Applicant: GLOBALFOUNDRIES, INC.Inventors: Jiehui Shu, Garo Jacques Derderian, Hui Zang, John Zhang, Haigou Huang, Jinping Liu
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Patent number: 10475791Abstract: First and second fin-type field effect transistors (finFETs) are formed laterally adjacent one another extending from a top surface of an isolation layer. The first finFET has a first fin structure and the second finFET has a second fin structure. An insulator layer is on the first fin structure and the second fin structure. A gate conductor intersects the first fin structure and the second fin structure, and at least the insulator layer separates the gate conductor from the first fin structure and the second fin structure. Source and drain structures are on the first fin structure and the second fin structure laterally adjacent the gate conductor. The first fin structure has sidewalls that include a step and the second fin structure has sidewalls that do not include the step. The step is approximately parallel to the surface of the isolation layer.Type: GrantFiled: May 31, 2018Date of Patent: November 12, 2019Assignee: GLOBALFOUNDRIES INC.Inventors: Hui Zang, Garo Jacques Derderian, Laertis Economikos, Chun Yu Wong, Jiehui Shu, Shesh Mani Pandey
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Patent number: 10418272Abstract: At least one method, apparatus and system providing semiconductor devices with relatively short gate heights but without a relatively high risk of contact-to-gate shorts. In embodiments, the method, apparatus, and system may provide contact formation by way of self-aligned contact processes.Type: GrantFiled: May 10, 2018Date of Patent: September 17, 2019Assignee: GLOBALFOUNDRIES INC.Inventors: Jiehui Shu, Garo Jacques Derderian, Hui Zang, John Zhang, Haigou Huang, Jinping Liu
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Publication number: 20180012760Abstract: Devices and methods of fabricating integrated circuit devices with reduced cell height are provided. One method includes, for instance: obtaining an intermediate semiconductor device having a substrate including a logic area and an SRAM area, a fin material layer, and a hardmask layer; depositing a mandrel over the logic area; depositing a sacrificial spacer layer; etching the sacrificial spacer layer to define a sacrificial set of vertical spacers; etching the hardmask layer; leaving a set of vertical hardmask spacers; depositing a first spacer layer; etching the first spacer layer to define a first set of vertical spacers over the logic area; depositing an SOH layer; etching an opening in the SOH layer over the SRAM area; depositing a second spacer layer; and etching the second spacer layer to define a second set of spacers over the SRAM area.Type: ApplicationFiled: August 11, 2017Publication date: January 11, 2018Applicant: GLOBALFOUNDRIES Inc.Inventors: Jiehui SHU, Daniel JAEGER, Garo Jacques DERDERIAN, Haifeng SHENG, Jinping LIU
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Patent number: 9761452Abstract: Devices and methods of fabricating integrated circuit devices with reduced cell height are provided. One method includes, for instance: obtaining an intermediate semiconductor device having a substrate including a logic area and an SRAM area, a fin material layer, and a hardmask layer; depositing a mandrel over the logic area; depositing a sacrificial spacer layer; etching the sacrificial spacer layer to define a sacrificial set of vertical spacers; etching the hardmask layer; leaving a set of vertical hardmask spacers; depositing a first spacer layer; etching the first spacer layer to define a first set of vertical spacers over the logic area; depositing an SOH layer; etching an opening in the SOH layer over the SRAM area; depositing a second spacer layer; and etching the second spacer layer to define a second set of spacers over the SRAM area.Type: GrantFiled: July 8, 2016Date of Patent: September 12, 2017Assignee: GLOBALFOUNDRIES Inc.Inventors: Jiehui Shu, Daniel Jaeger, Garo Jacques Derderian, Haifeng Sheng, Jinping Liu
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Patent number: 9754792Abstract: One illustrative method disclosed herein includes, among other things, forming an original fin-formation etch mask comprised of a plurality of original line-type features and removing at least a portion of at least one of the plurality of original line-type features so as to thereby define a modified fin-formation etch mask comprising the remaining portions of the plurality of original line-type features. The method also includes forming a conformal layer of material on the remaining portions of the plurality of original line-type features of the modified fin-formation etch mask and performing at least one etching process to remove at least portions of the conformal layer of material and to define a plurality of fin-formation trenches so as to thereby initially define a plurality of fins in the substrate.Type: GrantFiled: February 29, 2016Date of Patent: September 5, 2017Assignee: GLOBALFOUNDRIES Inc.Inventor: Garo Jacques Derderian
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Publication number: 20170250088Abstract: One illustrative method disclosed herein includes, among other things, forming an original fin-formation etch mask comprised of a plurality of original line-type features and removing at least a portion of at least one of the plurality of original line-type features so as to thereby define a modified fin-formation etch mask comprising the remaining portions of the plurality of original line-type features. The method also includes forming a conformal layer of material on the remaining portions of the plurality of original line-type features of the modified fin-formation etch mask and performing at least one etching process to remove at least portions of the conformal layer of material and to define a plurality of fin-formation trenches so as to thereby initially define a plurality of fins in the substrate.Type: ApplicationFiled: February 29, 2016Publication date: August 31, 2017Inventor: Garo Jacques Derderian
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Patent number: 9704759Abstract: Disclosed herein is a method of forming a CMOS integrated circuit product (comprised of first and second opposite type transistors) that includes forming a first spacer proximate both the first and second gate structures, forming an initial second spacer proximate the first spacer of the first transistor and a layer of second spacer material above the second transistor, and forming first raised epi semiconductor material source/drain regions for the first transistor. Thereafter, performing a first surface oxidation process so as to selectively form a hydrophilic material on exposed surfaces of the first raised epi semiconductor material and performing an etching process on both the transistors so as to remove the initial second spacer and the layer of second spacer material.Type: GrantFiled: September 4, 2015Date of Patent: July 11, 2017Assignee: GLOBALFOUNDRIES Inc.Inventors: Wen Pin Peng, Min-hwa Chi, Garo Jacques Derderian
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Publication number: 20170069547Abstract: Disclosed herein is a method of forming a CMOS integrated circuit product (comprised of first and second opposite type transistors) that includes forming a first spacer proximate both the first and second gate structures, forming an initial second spacer proximate the first spacer of the first transistor and a layer of second spacer material above the second transistor, and forming first raised epi semiconductor material source/drain regions for the first transistor. Thereafter, performing a first surface oxidation process so as to selectively form a hydrophilic material on exposed surfaces of the first raised epi semiconductor material and performing an etching process on both the transistors so as to remove the initial second spacer and the layer of second spacer material.Type: ApplicationFiled: September 4, 2015Publication date: March 9, 2017Inventors: Wen Pin Peng, Min-hwa Chi, Garo Jacques Derderian
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Patent number: 9385124Abstract: One method disclosed herein includes, among other things, forming a first spacer proximate gate structures of first and second transistors that are opposite type transistors, forming an initial second spacer proximate the first spacer of the first transistor and a layer of second spacer material above the second transistor, performing a timed, wet etching process on both of the transistors so as to completely remove the layer of second spacer material from the second transistor while leaving a reduced thickness second spacer positioned adjacent the first spacer of the first transistor, wherein the reduced thickness second spacer has a thickness that is less than an initial thickness of the initial second spacer, and forming a third spacer on and in contact with the first spacer of the second transistor.Type: GrantFiled: September 4, 2015Date of Patent: July 5, 2016Assignee: GLOBALFOUNDRIES Inc.Inventors: Wen Pin Peng, Min-hwa Chi, Garo Jacques Derderian
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Patent number: 9318440Abstract: Conductive contact structure of a circuit structures and methods of fabrication thereof are provided. The fabrication includes, for instance, providing at least one contact opening disposed over a semiconductor substrate; forming a carbon-rich contact liner material having a set carbon content conformally within the at least one contact opening disposed over the semiconductor substrate.Type: GrantFiled: July 14, 2015Date of Patent: April 19, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Huy Cao, Songkram Srivathanakul, Huang Liu, Garo Jacques Derderian, Boaz Alperson
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Publication number: 20150357285Abstract: Conductive contact structure of a circuit structures and methods of fabrication thereof are provided. The fabrication includes, for instance, providing at least one contact opening disposed over a semiconductor substrate; forming a carbon-rich contact liner material having a set carbon content conformally within the at least one contact opening disposed over the semiconductor substrate.Type: ApplicationFiled: July 14, 2015Publication date: December 10, 2015Applicant: GLOBALFOUNDRIES INC.Inventors: Huy CAO, Songkram SRIVATHANAKUL, Huang LIU, Garo Jacques DERDERIAN, Boaz ALPERSON
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Patent number: 9130019Abstract: Conductive contact structure of a circuit structures and methods of fabrication thereof are provided. The fabrication includes, for instance, providing at least one contact opening disposed over a semiconductor substrate; forming a carbon-rich contact liner material including a carbon-containing species and an elemental carbon disposed therein, the carbon-containing species and the elemental carbon together defining a set carbon content within the carbon-rich contact liner material; and depositing the carbon-rich contact liner material conformally within the at least one contact opening disposed over the semiconductor substrate.Type: GrantFiled: January 8, 2014Date of Patent: September 8, 2015Assignee: GLOBALFOUNDRIES INC.Inventors: Huy Cao, Songkram Srivathanakul, Huang Liu, Garo Jacques Derderian, Boaz Alperson
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Publication number: 20150194342Abstract: Conductive contact structure of a circuit structures and methods of fabrication thereof are provided. The fabrication includes, for instance, providing at least one contact opening disposed over a semiconductor substrate; forming a carbon-rich contact liner material including a carbon-containing species and an elemental carbon disposed therein, the carbon-containing species and the elemental carbon together defining a set carbon content within the carbon-rich contact liner material; and depositing the carbon-rich contact liner material conformally within the at least one contact opening disposed over the semiconductor substrate.Type: ApplicationFiled: January 8, 2014Publication date: July 9, 2015Applicant: GLOBALFOUNDRIES INC.Inventors: Huy CAO, Songkram SRIVATHANAKUL, Huang LIU, Garo Jacques DERDERIAN, Boaz ALPERSON