Abstract: An asynchronous anticontention circuit for a bi-directional bus. The asynchronous anticontention circuit comprises an anticontention circuit coupled to an asynchronous delay circuit. The anticontention circuit receives a driver select signal and generates a first signal and a second signal. The first signal and the second signal each have an active state and an inactive state. When the driver select signal is in a first logic state, the first signal is in the inactive state and the second signal is in the active state. When the driver select signal transitions from the first logic state to a second logic state, the anticontention circuit transitions the second signal from the active state to the inactive state. The asynchronous delay circuit couples the transition of the second signal to the anticontention circuit after a delay of time. After the delay of time, the anticontention circuit transitions the first signal from the inactive state to the active state.

Abstract: A synchronous contention prevention circuit for a bi-directional bus. The synchronous contention prevention circuit comprises a synchronous anticontention circuit coupled to a first input/output circuit. The synchronous anticontention circuit receives a driver select signal and a clock signal. The first input/output circuit has a first input coupled to the synchronous anticontention circuit and a first output. When the driver select signal is in a first logic state, the first input/output circuit is disabled from driving the first output. Subsequently, the driver select signal transitions from the first logic state to a second logic state. After the driver select signal transition to the second logic state, the synchronous anticontention circuit generates a first signal in response to a first transition of the clock signal. The synchronous anticontention circuit then generates a second signal in response to the first signal and a second transition of the clock signal.