Patents by Inventor Garrett Drapala

Garrett Drapala has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9003125
    Abstract: A technique for cache coherency is provided. A cache controller selects a first set from multiple sets in a congruence class based on a cache miss for a first transaction, and places a lock on the entire congruence class in which the lock prevents other transactions from accessing the congruence class. The cache controller designates in a cache directory the first set with a marked bit indicating that the first transaction is working on the first set, and the marked bit for the first set prevents the other transactions from accessing the first set within the congruence class. The cache controller removes the lock on the congruence class based on the marked bit being designated for the first set, and resets the marked bit for the first set to an unmarked bit based on the first transaction completing work on the first set in the congruence class.
    Type: Grant
    Filed: June 14, 2012
    Date of Patent: April 7, 2015
    Assignee: International Business Machines Corporation
    Inventors: Ekaterina M. Ambroladze, Michael Blake, Tim Bronson, Garrett Drapala, Pak-kin Mak, Arthur J. O'Neill
  • Publication number: 20130339622
    Abstract: A technique for cache coherency is provided. A cache controller selects a first set from multiple sets in a congruence class based on a cache miss for a first transaction, and places a lock on the entire congruence class in which the lock prevents other transactions from accessing the congruence class. The cache controller designates in a cache directory the first set with a marked bit indicating that the first transaction is working on the first set, and the marked bit for the first set prevents the other transactions from accessing the first set within the congruence class. The cache controller removes the lock on the congruence class based on the marked bit being designated for the first set, and resets the marked bit for the first set to an unmarked bit based on the first transaction completing work on the first set in the congruence class.
    Type: Application
    Filed: June 14, 2012
    Publication date: December 19, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ekaterina M. Ambroladze, Michael Blake, Tim Bronson, Garrett Drapala, Pak-kin Mak, Arthur J. O'Neill
  • Patent number: 7702972
    Abstract: SRAM macro sparing allows for full chip function despite the loss of one or more SRAM macros. The controls and data flow for any single macro within a protected group are made available to the spare or spares for that group. This allows a defective or failed SRAM macro to be shut off and replaced by a spare macro, dramatically increasing manufacturing yield and decreasing field replacement rates. The larger the protected group, the fewer the number of spares required for similar improvements in yield, but also the more difficult the task of making all the controls and dataflow available to the spare(s). In the case of the Level 2 Cache chip for the planned IBM Z6 computer, there are 4 protected groups with 192 SRAM macros per group. Each protected group is supplanted with an additional 2 spare SRAM macros, along with sparing controls and dataflow that allow either spare to replace any of the 192 protected SRAM macros.
    Type: Grant
    Filed: October 18, 2007
    Date of Patent: April 20, 2010
    Assignee: International Business Machines Corporation
    Inventors: Timothy Carl Bronson, Garrett Drapala, Hieu Trong Huynh, Patrick James Meaney
  • Publication number: 20090106607
    Abstract: SRAM macro sparing allows for full chip function despite the loss of one or more SRAM macros. The controls and data flow for any single macro within a protected group are made available to the spare or spares for that group. This allows a defective or failed SRAM macro to be shut off and replaced by a spare macro, dramatically increasing manufacturing yield and decreasing field replacement rates. The larger the protected group, the fewer the number of spares required for similar improvements in yield, but also the more difficult the task of making all the controls and dataflow available to the spare(s). In the case of the Level 2 Cache chip for the planned IBM Z6 computer, there are 4 protected groups with 192 SRAM macros per group. Each protected group is supplanted with an additional 2 spare SRAM macros, along with sparing controls and dataflow that allow either spare to replace any of the 192 protected SRAM macros.
    Type: Application
    Filed: October 18, 2007
    Publication date: April 23, 2009
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Timothy Carl Bronson, Garrett Drapala, Hieu Trong Huynh, Patrick James Meaney