Patents by Inventor Garrett M. Drapala
Garrett M. Drapala has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20160139831Abstract: A computing device is provided and includes a first physical memory device, a second physical memory device and a hypervisor configured to assign resources of the first and second physical memory devices to a logical partition. The hypervisor configures a dynamic memory relocation (DMR) mechanism to move entire storage increments currently processed by the logical partition between the first and second physical memory devices in a manner that is substantially transparent to the logical partition.Type: ApplicationFiled: November 19, 2014Publication date: May 19, 2016Inventors: Timothy C. Bronson, Garrett M. Drapala, Mark S. Farrell, Hieu T. Huynh, William J. Lewis, Pak-Kin Mak, Craig R. Walters
-
Publication number: 20160124854Abstract: A method, computer program product, and system for maintaining a proper ordering of a data steam that includes two or more sequentially ordered stores, the data stream being moved to a destination memory device, the two or more sequentially ordered stores including at least a first store and a second store, wherein the first store is rejected by the destination memory device. A computer-implemented method includes sending the first store to the destination memory device. A conditional request is sent to the destination memory device for approval to send the second store to the destination memory device, the conditional request dependent upon successful completion of the first store. The second store is cancelled responsive to receiving a reject response corresponding to the first store.Type: ApplicationFiled: November 5, 2014Publication date: May 5, 2016Inventors: Ekaterina M. Ambroladze, Garrett M. Drapala, Norbert Hagspiel, Sascha Junghans, Matthias Klein, Gary E. Strait
-
Publication number: 20160124653Abstract: A method, computer program product, and system for maintaining a proper ordering of a data steam that includes two or more sequentially ordered stores, the data stream being moved to a destination memory device, the two or more sequentially ordered stores including at least a first store and a second store, wherein the first store is rejected by the destination memory device. A computer-implemented method includes sending the first store to the destination memory device. A conditional request is sent to the destination memory device for approval to send the second store to the destination memory device, the conditional request dependent upon successful completion of the first store. The second store is cancelled responsive to receiving a reject response corresponding to the first store.Type: ApplicationFiled: November 19, 2015Publication date: May 5, 2016Inventors: Ekaterina M. Ambroladze, Garrett M. Drapala, Norbert Hagspiel, Sascha Junghans, Matthias Klein, Gary E. Strait
-
Patent number: 9323676Abstract: Embodiments relate to a non-data inclusive coherent (NIC) directory for a symmetric multiprocessor (SMP) of a computer. An aspect includes determining a first eviction entry of a highest-level cache in a multilevel caching structure of the first processor node of the SMP. Another aspect includes determining that the NIC directory is not full. Another aspect includes determining that the first eviction entry of the highest-level cache is owned by a lower-level cache in the multilevel caching structure. Another aspect includes, based on the NIC directory not being full and based on the first eviction entry of the highest-level cache being owned by the lower-level cache, installing an address of the first eviction entry of the highest-level cache in a first new entry in the NIC directory. Another aspect includes invalidating the first eviction entry in the highest-level cache.Type: GrantFiled: March 5, 2013Date of Patent: April 26, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Timothy C. Bronson, Garrett M. Drapala, Rebecca M. Gott, Pak-Kin Mak, Vijayalakshmi Srinivasan, Craig R. Walters
-
Publication number: 20160110288Abstract: A cache coherency management facility to reduce latency in granting exclusive access to a cache in certain situations. A node requests exclusive access to a cache line of the cache. The node is in one region of nodes of a plurality of regions of nodes. The one region of nodes includes the node requesting exclusive access and another node of the computing environment, in which the node and the another node are local to one another as defined by a predetermined criteria. The node requesting exclusive access checks a locality cache coherency state of the another node, the locality cache coherency state being specific to the another node and indicating whether the another node has access to the cache line. Based on the checking indicating that the another node has access to the cache line, a determination is made that the node requesting exclusive access is to be granted exclusive access to the cache line.Type: ApplicationFiled: September 7, 2015Publication date: April 21, 2016Inventors: Timothy C. Bronson, Garrett M. Drapala, Pak-kin Mak, Vesselina K. Papazova, Hanno Ulrich
-
Publication number: 20160110287Abstract: A cache coherency management facility to reduce latency in granting exclusive access to a cache in certain situations. A node requests exclusive access to a cache line of the cache. The node is in one region of nodes of a plurality of regions of nodes. The one region of nodes includes the node requesting exclusive access and another node of the computing environment, in which the node and the another node are local to one another as defined by a predetermined criteria. The node requesting exclusive access checks a locality cache coherency state of the another node, the locality cache coherency state being specific to the another node and indicating whether the another node has access to the cache line. Based on the checking indicating that the another node has access to the cache line, a determination is made that the node requesting exclusive access is to be granted exclusive access to the cache line.Type: ApplicationFiled: October 20, 2014Publication date: April 21, 2016Inventors: Timothy C. Bronson, Garrett M. Drapala, Pak-kin Mak, Vesselina K. Papazova, Hanno Ulrich
-
Patent number: 9299456Abstract: Embodiments relate to matrix and compression-based error detection. An aspect includes summing, by each of a first plurality of summing modules of a first compressor, a respective row of a matrix, the matrix comprising a plurality of rows and a plurality of columns of output bits of a circuit under test wherein each output bit of the circuit under test comprises an element of the matrix, and is a member of a row of a column that is orthogonal to the row. Another aspect includes summing, by each of a second plurality of summing modules of a second compressor, a respective column of output bits of the matrix. Yet another aspect includes determining a presence of an error in the circuit under test based at least one of an output of the first compressor and an output of the second compressor.Type: GrantFiled: September 30, 2014Date of Patent: March 29, 2016Assignee: International Business Machines CorporationInventors: Garrett M. Drapala, Gary E. Strait
-
Patent number: 9292445Abstract: Embodiments relate to a non-data inclusive coherent (NIC) directory for a symmetric multiprocessor (SMP) of a computer. An aspect includes determining a first eviction entry of a highest-level cache in a multilevel caching structure of the first processor node of the SMP. Another aspect includes determining that the NIC directory is not full. Another aspect includes determining that the first eviction entry of the highest-level cache is owned by a lower-level cache in the multilevel caching structure. Another aspect includes, based on the NIC directory not being full and based on the first eviction entry of the highest-level cache being owned by the lower-level cache, installing an address of the first eviction entry of the highest-level cache in a first new entry in the NIC directory. Another aspect includes invalidating the first eviction entry in the highest-level cache.Type: GrantFiled: September 30, 2014Date of Patent: March 22, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Timothy C. Bronson, Garrett M. Drapala, Rebecca M. Gott, Pak-kin Mak, Vijayalakshmi Srinivasan, Craig R. Walters
-
Patent number: 9268660Abstract: Embodiments relate to matrix and compression-based error detection. An aspect includes summing, by each of a first plurality of summing modules of a first compressor, a respective row of a matrix, the matrix comprising a plurality of rows and a plurality of columns of output bits of a circuit under test wherein each output bit of the circuit under test comprises an element of the matrix, and is a member of a row of a column that is orthogonal to the row. Another aspect includes summing, by each of a second plurality of summing modules of a second compressor, a respective column of output bits of the matrix. Yet another aspect includes determining a presence of an error in the circuit under test based at least one of an output of the first compressor and an output of the second compressor.Type: GrantFiled: March 12, 2014Date of Patent: February 23, 2016Assignee: International Business Machines CorporationInventors: Garrett M. Drapala, Gary E. Strait
-
Patent number: 9244851Abstract: A technique for cache coherency is provided. A cache controller selects a first set from multiple sets in a congruence class based on a cache miss for a first transaction, and places a lock on the entire congruence class in which the lock prevents other transactions from accessing the congruence class. The cache controller designates in a cache directory the first set with a marked bit indicating that the first transaction is working on the first set, and the marked bit for the first set prevents the other transactions from accessing the first set within the congruence class. The cache controller removes the lock on the congruence class based on the marked bit being designated for the first set, and resets the marked bit for the first set to an unmarked bit based on the first transaction completing work on the first set in the congruence class.Type: GrantFiled: January 22, 2013Date of Patent: January 26, 2016Assignee: International Business Machines CorporationInventors: Ekaterina M. Ambroladze, Michael A. Blake, Timothy C. Bronson, Garrett M. Drapala, Pak-kin Mak, Arthur J. O'Neill
-
Publication number: 20150261638Abstract: Embodiments relate to matrix and compression-based error detection. An aspect includes summing, by each of a first plurality of summing modules of a first compressor, a respective row of a matrix, the matrix comprising a plurality of rows and a plurality of columns of output bits of a circuit under test wherein each output bit of the circuit under test comprises an element of the matrix, and is a member of a row of a column that is orthogonal to the row. Another aspect includes summing, by each of a second plurality of summing modules of a second compressor, a respective column of output bits of the matrix. Yet another aspect includes determining a presence of an error in the circuit under test based at least one of an output of the first compressor and an output of the second compressor.Type: ApplicationFiled: September 30, 2014Publication date: September 17, 2015Inventors: Garrett M. Drapala, Gary E. Strait
-
Publication number: 20150260792Abstract: Embodiments relate to matrix and compression-based error detection. An aspect includes summing, by each of a first plurality of summing modules of a first compressor, a respective row of a matrix, the matrix comprising a plurality of rows and a plurality of columns of output bits of a circuit under test wherein each output bit of the circuit under test comprises an element of the matrix, and is a member of a row of a column that is orthogonal to the row. Another aspect includes summing, by each of a second plurality of summing modules of a second compressor, a respective column of output bits of the matrix. Yet another aspect includes determining a presence of an error in the circuit under test based at least one of an output of the first compressor and an output of the second compressor.Type: ApplicationFiled: March 12, 2014Publication date: September 17, 2015Applicant: International Business Machines CorporationInventors: Garrett M. Drapala, Gary E. Strait
-
Patent number: 8972664Abstract: Embodiments relate to accessing a cache line on a multi-level cache system having a system memory. Based on a request for exclusive ownership of a specific cache line at the local node, requests are concurrently sent to the system memory and remote nodes of the plurality of nodes for the specific cache line by the local node. The specific cache line is found in a specific remote node. The specific remote node is one of the remote nodes. The specific cache line is removed from the specific remote node for exclusive ownership by another node. Based on the specified node having the specified cache line in ghost state, any subsequent fetch request is initiated for the specific cache line from the specific node encounters the ghost state. When the ghost state is encountered, the subsequent fetch request is directed only to nodes of the plurality of nodes.Type: GrantFiled: March 11, 2013Date of Patent: March 3, 2015Assignee: International Business Machines CorporationInventors: Timothy C. Bronson, Garrett M. Drapala, Michael A. Blake, Craig R. Walters, Pak-Kin Mak
-
Publication number: 20150058569Abstract: Embodiments relate to a non-data inclusive coherent (NIC) directory for a symmetric multiprocessor (SMP) of a computer. An aspect includes determining a first eviction entry of a highest-level cache in a multilevel caching structure of the first processor node of the SMP. Another aspect includes determining that the NIC directory is not full. Another aspect includes determining that the first eviction entry of the highest-level cache is owned by a lower-level cache in the multilevel caching structure. Another aspect includes, based on the NIC directory not being full and based on the first eviction entry of the highest-level cache being owned by the lower-level cache, installing an address of the first eviction entry of the highest-level cache in a first new entry in the NIC directory. Another aspect includes invalidating the first eviction entry in the highest-level cache.Type: ApplicationFiled: September 30, 2014Publication date: February 26, 2015Inventors: Timothy C. Bronson, Garrett M. Drapala, Rebecca M. Gott, Pak-kin Mak, Vijayalakshmi Srinivasan, Craig R. Walters
-
Patent number: 8918587Abstract: Embodiments relate to accessing a cache line on a multi-level cache system having a system memory. Based on a request for exclusive ownership of a specific cache line at the local node, requests are concurrently sent to the system memory and remote nodes of the plurality of nodes for the specific cache line by the local node. The specific cache line is found in a specific remote node. The specific remote node is one of the remote nodes. The specific cache line is removed from the specific remote node for exclusive ownership by another node. Based on the specified node having the specified cache line in ghost state, any subsequent fetch request is initiated for the specific cache line from the specific node encounters the ghost state. When the ghost state is encountered, the subsequent fetch request is directed only to nodes of the plurality of nodes.Type: GrantFiled: June 13, 2012Date of Patent: December 23, 2014Assignee: International Business Machines CorporationInventors: Timothy C. Bronson, Garrett M. Drapala, Michael A. Blake, Craig R. Walters, Pak-Kin Mak
-
Publication number: 20140258621Abstract: Embodiments relate to a non-data inclusive coherent (NIC) directory for a symmetric multiprocessor (SMP) of a computer. An aspect includes determining a first eviction entry of a highest-level cache in a multilevel caching structure of the first processor node of the SMP. Another aspect includes determining that the NIC directory is not full. Another aspect includes determining that the first eviction entry of the highest-level cache is owned by a lower-level cache in the multilevel caching structure. Another aspect includes, based on the NIC directory not being full and based on the first eviction entry of the highest-level cache being owned by the lower-level cache, installing an address of the first eviction entry of the highest-level cache in a first new entry in the NIC directory. Another aspect includes invalidating the first eviction entry in the highest-level cache.Type: ApplicationFiled: March 5, 2013Publication date: September 11, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Timothy C. Bronson, Garrett M. Drapala, Rebecca M. Gott, Pak-Kin Mak, Vijayalakshmi Srinivasan, Craig R. Walters
-
Patent number: 8762651Abstract: Maintaining cache coherence in a multi-node, symmetric multiprocessing computer, the computer composed of a plurality of compute nodes, including, broadcasting upon a cache miss by the first compute node to other compute nodes a request for the cache line; if at least two of the compute nodes has a correct copy of the cache line, selecting which compute node is to transmit the correct copy of the cache line to the first node, and transmitting from the selected compute node to the first node the correct copy of the cache line; and updating by each node the state of the cache line in each node, in dependence upon one or more of the states of the cache line in all the nodes.Type: GrantFiled: June 23, 2010Date of Patent: June 24, 2014Assignee: International Business Machines CorporationInventors: Michael A. Blake, Garrett M. Drapala, Pak-Kin Mak, Vesselina K. Papazova, Craig R. Walters
-
Patent number: 8688880Abstract: Serializing instructions in a multiprocessor system includes receiving a plurality of processor requests at a central point in the multiprocessor system. Each of the plurality of processor requests includes a needs register having a requestor needs switch and a resource needs switch. The method also includes establishing a tail switch indicating the presence of the plurality of processor requests at the central point, establishing a sequential order of the plurality of processor requests, and processing the plurality of processor requests at the central point in the sequential order.Type: GrantFiled: June 23, 2010Date of Patent: April 1, 2014Assignee: International Business Machines CorporationInventors: Garrett M. Drapala, Michael A. Blake, Timothy C. Bronson, Lawrence D. Curley
-
Publication number: 20130339608Abstract: Embodiments relate to accessing a cache line on a multi-level cache system having a system memory. Based on a request for exclusive ownership of a specific cache line at the local node, requests are concurrently sent to the system memory and remote nodes of the plurality of nodes for the specific cache line by the local node. The specific cache line is found in a specific remote node. The specific remote node is one of the remote nodes. The specific cache line is removed from the specific remote node for exclusive ownership by another node. Based on the specified node having the specified cache line in ghost state, any subsequent fetch request is initiated for the specific cache line from the specific node encounters the ghost state. When the ghost state is encountered, the subsequent fetch request is directed only to nodes of the plurality of nodes.Type: ApplicationFiled: June 13, 2012Publication date: December 19, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Timothy C. Bronson, Garrett M. Drapala, Michael A. Blake, Craig R. Walters, Pak-Kin Mak
-
Publication number: 20130339623Abstract: A technique for cache coherency is provided. A cache controller selects a first set from multiple sets in a congruence class based on a cache miss for a first transaction, and places a lock on the entire congruence class in which the lock prevents other transactions from accessing the congruence class. The cache controller designates in a cache directory the first set with a marked bit indicating that the first transaction is working on the first set, and the marked bit for the first set prevents the other transactions from accessing the first set within the congruence class. The cache controller removes the lock on the congruence class based on the marked bit being designated for the first set, and resets the marked bit for the first set to an unmarked bit based on the first transaction completing work on the first set in the congruence class.Type: ApplicationFiled: January 22, 2013Publication date: December 19, 2013Applicant: International Business Machines CorporationInventors: Ekaterina M. Ambroladze, Michael A. Blake, Timothy C. Bronson, Garrett M. Drapala, Pak-kin Mak, Arthur J. O'Neill