Patents by Inventor Garrett Storaska
Garrett Storaska has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 7871529Abstract: Novel applications of nanocoil technology and novel methods of fabricating nanocoils for use in such applications and others. Such applications include microscopic electro-mechanical systems (MEMS) devices including nanocoil mirrors, nanocoil actuators and nanocoil antenna arrays. Inductors or traveling wave tubes fabricated from nanocoils are also included. A method for fabricating nanocoils with a desired pitch includes determining a desired pitch for fabricated nanocoil, selecting coiling arm orientation in which coiling arm orientation is arm angle between coiling arm an crystalline orientation of underlying substrate, whereby coiling arm orientation affects pitch of fabricated nanocoil, patterning coiling arm structure with selected coiling arm orientation, and, releasing coiling arm, whereby fabricated nanocoil is formed.Type: GrantFiled: January 26, 2010Date of Patent: January 18, 2011Assignee: Northrop Grumman Systems CorporationInventors: Garrett A. Storaska, Robert S. Howell
-
Patent number: 7868358Abstract: A device includes a coiling layer, a circuit device layer and active microelectronic circuitry fabricated on the circuit device layer. The coiling layer is formed onto a surface of and coupled to the circuit device layer. The coiling layer having intrinsic stresses which cause coiling of the coiling layer and the circuit device layer including the microelectronic circuitry as the circuit device layer is released from an underlying substrate. A coiled circuit device is formed.Type: GrantFiled: January 17, 2007Date of Patent: January 11, 2011Assignee: Northrop Grumman Systems CorporationInventors: Joseph Smith, Harvey C. Nathanson, Robert S. Howell, Christopher F. Kirby, Garrett A. Storaska
-
Patent number: 7795647Abstract: A curled transistor comprises a coiled semiconductor substrate having a plurality of concentrically curled layers. Source and drain regions are configured on a portion of the coiled semiconductor substrate, and a gate dielectric is positioned between the source and drain regions. A first set of metallic contacts electrically couple to the source region on the coiled semiconductor substrate and a second set of metallic contacts electrically couple to the drain region on the coiled semiconductor substrate.Type: GrantFiled: March 29, 2007Date of Patent: September 14, 2010Assignee: Northrop Grumman Systems CorporationInventors: Garrett A. Storaska, Robert S. Howell, Harvey C. Nathanson, Francis William Hopwood
-
Publication number: 20100224957Abstract: Novel applications of nanocoil technology and novel methods of fabricating nanocoils for use in such applications and others. Such applications include microscopic electro-mechanical systems (MEMS) devices including nanocoil mirrors, nanocoil actuators and nanocoil antenna arrays. Inductors or traveling wave tubes fabricated from nanocoils are also included. A method for fabricating nanocoils with a desired pitch includes determining a desired pitch for fabricated nanocoil, selecting coiling arm orientation in which coiling arm orientation is arm angle between coiling arm an crystalline orientation of underlying substrate, whereby coiling arm orientation affects pitch of fabricated nanocoil, patterning coiling arm structure with selected coiling arm orientation, and, releasing coiling arm, whereby fabricated nanocoil is formed.Type: ApplicationFiled: January 26, 2010Publication date: September 9, 2010Inventors: Garrett A. STORASKA, Robert S. Howell
-
Patent number: 7710235Abstract: Novel applications of nanocoil technology and novel methods of fabricating nanocoils for use in such applications and others. Such applications include inductors or traveling wave tubes fabricated from spiral nanocoils. Such applications includes inductors or traveling wave tubes fabricated from a method for fabricating nanocoils with a desired pitch. Such a method includes determining a desired pitch for fabricated nanocoil, selecting coiling arm orientation in which coiling arm orientation is arm angle between coiling arm an crystalline orientation of underlying substrate, whereby coiling arm orientation affects pitch of fabricated nanocoil, patterning coiling arm structure with selected coiling arm orientation, and, releasing coiling arm, whereby fabricated nanocoil is formed.Type: GrantFiled: September 21, 2006Date of Patent: May 4, 2010Assignee: Northrop Grumman Systems CorporationInventors: Garrett A. Storaska, Robert S. Howell
-
Patent number: 7601620Abstract: Improved nanocoils, systems and methods for fabricating nanocoils. Embodiments enable wet etching techniques for releasing coiling arm structures and forming nanocoils. A method for fabricating nanocoils includes providing a silicon-on-insulator (SOI) wafer in which SOI wafer includes a buried oxide layer, patterning one or more devices onto a silicon device layer on top of the buried oxide layer, depositing a tensile stressed layer on the silicon device layer so that stressed layer and silicon device layer form a stressed coiling bi-layer, patterning a coiling arm structure on the stressed coiling bi-layer, depositing a metal encapsulation layer on the stressed coiling bi-layer, and releasing the coiling arm structure so that coiling arm coils to form nanocoil.Type: GrantFiled: September 21, 2006Date of Patent: October 13, 2009Assignee: Northrop Grumman Systems CorporationInventors: Garrett A. Storaska, Robert S. Howell
-
Patent number: 7514301Abstract: A method for fabricating nanocoils and improved nanocoils fabricated therefrom. Embodiments of the method utilizing deep reactive ion etching (DRIE). A method for fabricating nanocoils includes providing a silicon-on-insulator (SOI) wafer, in which SOI wafer includes buried oxide layer, patterning one or more devices into a layer of silicon on top of the buried oxide layer, depositing tensile stressed nitride layer on the top silicon layer, patterning coiling arm structure on top silicon layer, patterning an overlapping etch window mask on bottom side of SOI wafer using, in which patterning overlapping etch window mask removes SOI wafer and exposes buried oxide layer in width greater than coiling arm structure, and releasing coiling arm structure so that coiling arm coils to form nanocoil. In embodiments, DRIE is utilized to pattern the overlapping etch window mask.Type: GrantFiled: September 21, 2006Date of Patent: April 7, 2009Assignee: Northrop Grumman CorporationInventors: Garrett A. Storaska, Robert S. Howell
-
Publication number: 20090053860Abstract: A method for fabricating nanocoils and improved nanocoils fabricated therefrom. Embodiments of the method utilizing deep reactive ion etching (DRIE). A method for fabricating nanocoils includes providing a silicon-on-insulator (SOI) wafer, in which SOI wafer includes buried oxide layer, patterning one or more devices into a layer of silicon on top of the buried oxide layer, depositing tensile stressed nitride layer on the top silicon layer, patterning coiling arm structure on top silicon layer, patterning an overlapping etch window mask on bottom side of SOI wafer using, in which patterning overlapping etch window mask removes SOI wafer and exposes buried oxide layer in width greater than coiling arm structure, and releasing coiling arm structure so that coiling arm coils to form nanocoil. In embodiments, DRIE is utilized to pattern the overlapping etch window mask.Type: ApplicationFiled: September 21, 2006Publication date: February 26, 2009Inventors: Garrett A. Storaska, Robert S. Howell
-
Patent number: 7488994Abstract: A coiled circuit device is produced by forming a circuit layer on a substrate. Optional insulator layers may be disposed above and below the circuit layer. The circuit layer, which may be memory, control, or other circuitry, is released from the substrate such that it coils into a dense, coiled device. A stressed coiling layer may be included which effects coiling when the circuit layer is released.Type: GrantFiled: June 7, 2004Date of Patent: February 10, 2009Assignee: Northrop Grumman CorporationInventors: Harvey C. Nathanson, Robert S. Howell, Garrett A. Storaska
-
Publication number: 20070284633Abstract: A curled transistor comprises a coiled semiconductor substrate having a plurality of concentrically curled layers. Source and drain regions are configured on a portion of the coiled semiconductor substrate, and a gate dielectric is positioned between the source and drain regions. A first set of metallic contacts electrically couple to the source region on the coiled semiconductor substrate and a second set of metallic contacts electrically couple to the drain region on the coiled semiconductor substrate.Type: ApplicationFiled: March 29, 2007Publication date: December 13, 2007Inventors: Garrett Storaska, Robert Howell, Harvey Nathanson, Francis Hopwood
-
Publication number: 20070165293Abstract: Novel applications of nanocoil technology and novel methods of fabricating nanocoils for use in such applications and others. Such applications include microscopic electro-mechanical systems (MEMS) devices including nanocoil mirrors, nanocoil actuators and nanocoil antenna arrays. Inductors or traveling wave tubes fabricated from nanocoils are also included. A method for fabricating nanocoils with a desired pitch includes determining a desired pitch for fabricated nanocoil, selecting coiling arm orientation in which coiling arm orientation is arm angle between coiling arm an crystalline orientation of underlying substrate, whereby coiling arm orientation affects pitch of fabricated nanocoil, patterning coiling arm structure with selected coiling arm orientation, and, releasing coiling arm, whereby fabricated nanocoil is formed.Type: ApplicationFiled: September 21, 2006Publication date: July 19, 2007Inventors: Garrett Storaska, Robert Howell
-
Publication number: 20070123054Abstract: Improved nanocoils, systems and methods for fabricating nanocoils. Embodiments enable wet etching techniques for releasing coiling arm structures and forming nanocoils. A method for fabricating nanocoils includes providing a silicon-on-insulator (SOI) wafer in which SOI wafer includes a buried oxide layer, patterning one or more devices onto a silicon device layer on top of the buried oxide layer, depositing a tensile stressed layer on the silicon device layer so that stressed layer and silicon device layer form a stressed coiling bi-layer, patterning a coiling arm structure on the stressed coiling bi-layer, depositing a metal encapsulation layer on the stressed coiling bi-layer, and releasing the coiling arm structure so that coiling arm coils to form nanocoil.Type: ApplicationFiled: September 21, 2006Publication date: May 31, 2007Inventors: Garrett Storaska, Robert Howell
-
Publication number: 20070117392Abstract: A device includes a coiling layer, a circuit device layer and active microelectronic circuitry fabricated on the circuit device layer. The coiling layer is formed onto a surface of and coupled to the circuit device layer. The coiling layer having intrinsic stresses which cause coiling of the coiling layer and the circuit device layer including the microelectronic circuitry as the circuit device layer is released from an underlying substrate. A coiled circuit device is formed.Type: ApplicationFiled: January 17, 2007Publication date: May 24, 2007Inventors: Joseph Smith, Harvey Nathanson, Robert Howell, Christopher Kirby, Garrett Storaska
-
Patent number: 7164811Abstract: A small portable “pocket pen size” projector/image grabber device for allowing an individual to gather, share and exploit information in a projected format in real time, day or night, with other individuals on demand. An ultra high density MEMS mirror display array provides a 1024×768 line projection display. An on-axis 512×384 color CCD imager is also included resulting in a digitally-aligned image capture and overlay display capability. A sequentially-addressed three color chip laser and low cost plastic optics provides full color high resolution bright displays for group viewing. 3-D color imaging is also provided by a binocular attachment to the device which permits the capturing of three-dimensional imagery.Type: GrantFiled: June 30, 2004Date of Patent: January 16, 2007Assignee: Northrop Grumman CorporationInventors: Harvey C. Nathanson, Robert S. Howell, Ragini Saxena, Garrett A. Storaska
-
Patent number: 7119942Abstract: A micro-electrical mechanical system (MEMS) mirror assembly including an array of micro-mirrors formed on a substrate and having springs on one side and which angularly tilt between ON and OFF states in response to an electrostatic force generated by a voltage applied to an electrode located on the substrate. At least one, but preferably two springs in the form of two thin strips of metal attach to post(s) at the side edge of the mirror and act as springs which provide a restoring force when the mirror is tilted between an OFF state which occurs when the mirror is flat relative to the substrate with no voltage applied, and in the ON state when the mirror is tilted when a voltage is applied.Type: GrantFiled: June 30, 2004Date of Patent: October 10, 2006Assignee: Northrop Gruman CorporationInventors: Harvey C. Nathanson, Robert S. Howell, Garrett A. Storaska, John B. Goodell, Stephen D. Vancampen
-
Publication number: 20060012850Abstract: A micro-electrical mechanical system (MEMS) mirror assembly including an array of micro-mirrors formed on a substrate and having springs on one side and which angularly tilt between ON and OFF states in response to an electrostatic force generated by a voltage applied to an electrode located on the substrate. At least one, but preferably two springs in the form of two thin strips of metal attach to post(s) at the side edge of the mirror and act as springs which provide a restoring force when the mirror is tilted between an OFF state which occurs when the mirror is flat relative to the substrate with no voltage applied, and in the ON state when the mirror is tilted when a voltage is applied.Type: ApplicationFiled: June 30, 2004Publication date: January 19, 2006Inventors: Harvey Nathanson, Robert Howell, Garrett Storaska, John Goodell, Stephen Vancampen
-
Publication number: 20050280628Abstract: A high resolution pen-sized projector for controlling the position and size of an image generated by a closed loop control system consists of four major system components including: a virtual VGA display located inside of a XGA display, a position acquisition system, a displacement compensating control system to determine correct position of the VGA display inside of the XGA display, and a dark display area of the background portion of the XGA display.Type: ApplicationFiled: May 11, 2005Publication date: December 22, 2005Applicant: Northrop Grumman Corp.Inventors: Charles Adams, Harvey Nathanson, Robert Howell, Garrett Storaska, William Hall
-
Publication number: 20050206770Abstract: A small portable “pocket pen size” projector/image grabber device for allowing an individual to gather, share and exploit information in a projected format in real time, day or night, with other individuals on demand. An ultra high density MEMS mirror display array provides a 1024×768 line projection display. An on-axis 512×384 color CCD imager is also included resulting in a digitally-aligned image capture and overlay display capability. A sequentially-addressed three color chip laser and low cost plastic optics provides full color high resolution bright displays for group viewing. 3-D color imaging is also provided by a binocular attachment to the device which permits the capturing of three-dimensional imagery.Type: ApplicationFiled: June 30, 2004Publication date: September 22, 2005Inventors: Harvey Nathanson, Robert Howell, Ragini Saxena, Garrett Storaska
-
Publication number: 20050013151Abstract: A coiled circuit device is produced by forming a circuit layer on a substrate. Optional insulator layers may be disposed above and below the circuit layer. The circuit layer, which may be memory, control, or other circuitry, is released from the substrate such that it coils into a dense, coiled device. A stressed coiling layer may be included which effects coiling when the circuit layer is released.Type: ApplicationFiled: June 7, 2004Publication date: January 20, 2005Inventors: Harvey Nathanson, Robert Howell, Garrett Storaska