Patents by Inventor Garry Epps
Garry Epps has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7881617Abstract: An optical packet processor includes one or more optical packet inputs that receive asynchronous optical packets. An optical packet interconnect directs the optical packets from the different optical packet inputs to different optical packet outputs. The optical packets are buffered either before or after being directed from the inputs to the different outputs. Problems associated with optical buffering are overcome by synchronizing the asynchronous optical packets with the optical packet buffers. The novel optical buffer architectures described also reduce or eliminate the use of certain high cost optical components.Type: GrantFiled: April 24, 2006Date of Patent: February 1, 2011Assignee: Cisco Technology, Inc.Inventors: Earl T. Cohen, Garry Epps
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Patent number: 7835649Abstract: Asynchronous optical data is aligned with synchronous convergence points in an optical packet switching system. The convergence points can be any place where data enters an optical packet switching element, buffer stage, switch fabric, etc. The arrival time for data approaching the convergence point is compared with a reference signal associated with the upcoming convergence point. The comparison is used to identify the amount of time-shift required to align the approaching data with the reference signal. Control information is derived according to the comparison and used to control an optical data aligner that synchronizes the data with the convergence point.Type: GrantFiled: February 24, 2006Date of Patent: November 16, 2010Assignee: Cisco Technology, Inc.Inventors: Garry Epps, Earl T. Cohen
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Publication number: 20070283073Abstract: A port adapter for connecting zero or more network interfaces to a host system having a SPI-4 bus is disclosed. The port adapter comprises zero or more network interfaces; a SPI-4 bus coupled to a host system to provide a communication channel between the host and the network interfaces; a control bus coupled to the host system for controlling and monitoring the port adapter; and interface logic that interfaces the SPI-4 bus and the control bus to the network interfaces. Methods are provided for selecting and using one of a small plurality of different packet formats for various networking technologies, so that the port adapter can hide details of the technology that it handles from the host system, and for operating the host system's SPI-4 bus at one of several speeds based on bandwidth requirements of the port adapter.Type: ApplicationFiled: June 12, 2007Publication date: December 6, 2007Inventors: David Doak, Garry Epps, Guy Fedorkow, Mark Gustlin, Steven Holmes, Randall Johnson, Promode Nedungadi, Mohammed Tatar
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Publication number: 20070201877Abstract: Asynchronous optical data is aligned with synchronous convergence points in an optical packet switching system. The convergence points can be any place where data enters an optical packet switching element, buffer stage, switch fabric, etc. The arrival time for data approaching the convergence point is compared with a reference signal associated with the upcoming convergence point. The comparison is used to identify the amount of time-shift required to align the approaching data with the reference signal. Control information is derived according to the comparison and used to control an optical data aligner that synchronizes the data with the convergence point.Type: ApplicationFiled: February 24, 2006Publication date: August 30, 2007Inventors: Garry Epps, Earl Cohen
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Publication number: 20070201870Abstract: An optical packet processor includes one or more optical packet inputs that receive asynchronous optical packets. An optical packet interconnect directs the optical packets from the different optical packet inputs to different optical packet outputs. The optical packets are buffered either before or after being directed from the inputs to the different outputs. Problems associated with optical buffering are overcome by synchronizing the asynchronous optical packets with the optical packet buffers. The novel optical buffer architectures described also reduce or eliminate the use of certain high cost optical components.Type: ApplicationFiled: April 24, 2006Publication date: August 30, 2007Inventors: Earl Cohen, Garry Epps
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Publication number: 20070195778Abstract: An architecture for a line card in a network routing device is provided. The line card architecture provides a bi-directional interface between the routing device and a network, both receiving packets from the network and transmitting the packets to the network through one or more connecting ports. In both the receive and transmit path, packets processing and routing in a multi-stage, parallel pipeline that can operate on several packets at the same time to determine each packet's routing destination is provided. Once a routing destination determination is made, the line card architecture provides for each received packet to be modified to contain new routing information and additional header data to facilitate packet transmission through the switching fabric. The line card architecture further provides for the use of bandwidth management techniques in order to buffer and enqueue each packet for transmission through the switching fabric to a corresponding destination port.Type: ApplicationFiled: March 6, 2006Publication date: August 23, 2007Inventors: Mohammed Tatar, Garry Epps, Oded Trainin, Eyal Oren, Cedrik Begin
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Publication number: 20070195777Abstract: An architecture for a line card in a network routing device is provided. The line card architecture provides a bi-directional interface between the routing device and a network, both receiving packets from the network and transmitting the packets to the network through one or more connecting ports. In both the receive and transmit path, packets processing and routing in a multi-stage, parallel pipeline that can operate on several packets at the same time to determine each packet's routing destination is provided. Once a routing destination determination is made, the line card architecture provides for each received packet to be modified to contain new routing information and additional header data to facilitate packet transmission through the switching fabric. The line card architecture further provides for the use of bandwidth management techniques in order to buffer and enqueue each packet for transmission through the switching fabric to a corresponding destination port.Type: ApplicationFiled: March 6, 2006Publication date: August 23, 2007Inventors: Mohammed Tatar, Garry Epps, Oded Trainin, Eyal Oren, Cedrik Begin
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Publication number: 20070195761Abstract: An architecture for a line card in a network routing device is provided. The line card architecture provides a bi-directional interface between the routing device and a network, both receiving packets from the network and transmitting the packets to the network through one or more connecting ports. In both the receive and transmit path, packets processing and routing in a multi-stage, parallel pipeline that can operate on several packets at the same time to determine each packet's routing destination is provided. Once a routing destination determination is made, the line card architecture provides for each received packet to be modified to contain new routing information and additional header data to facilitate packet transmission through the switching fabric. The line card architecture further provides for the use of bandwidth management techniques in order to buffer and enqueue each packet for transmission through the switching fabric to a corresponding destination port.Type: ApplicationFiled: March 1, 2006Publication date: August 23, 2007Inventors: Mohammed Tatar, Garry Epps, Oded Trainin, Eyal Oren, Cedrik Begin
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Publication number: 20070195773Abstract: An architecture for a line card in a network routing device is provided. The line card architecture provides a bi-directional interface between the routing device and a network, both receiving packets from the network and transmitting the packets to the network through one or more connecting ports. In both the receive and transmit path, packets processing and routing in a multi-stage, parallel pipeline that can operate on several packets at the same time to determine each packet's routing destination is provided. Once a routing destination determination is made, the line card architecture provides for each received packet to be modified to contain new routing information and additional header data to facilitate packet transmission through the switching fabric. The line card architecture further provides for the use of bandwidth management techniques in order to buffer and enqueue each packet for transmission through the switching fabric to a corresponding destination port.Type: ApplicationFiled: February 21, 2006Publication date: August 23, 2007Inventors: Mohammed Tatar, Garry Epps, Oded Trainin, Eyal Oren, Cedrik Begin
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Publication number: 20060277346Abstract: A port adapter for connecting zero or more network interfaces to a host system having a SPI-4 bus is disclosed. The port adapter comprises zero or more network interfaces; a SPI-4 bus coupled to a host system to provide a communication channel between the host and the network interfaces; a control bus coupled to the host system for controlling and monitoring the port adapter; and interface logic that interfaces the SPI-4 bus and the control bus to the network interfaces. Methods are provided for selecting and using one of a small plurality of different packet formats for various networking technologies, so that the port adapter can hide details of the technology that it handles from the host system, and for operating the host system's SPI-4 bus at one of several speeds based on bandwidth requirements of the port adapter.Type: ApplicationFiled: August 11, 2006Publication date: December 7, 2006Inventors: David Doak, Garry Epps, Guy Fedorkow, Mark Gustlin, Steven Holmes, Randall Johnson, Promode Nedungadi, John Prokopik, Mohammed Tatar, Michael Taylor
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Publication number: 20060050690Abstract: A pipelined linecard architecture for receiving, modifying, switching, buffering, queuing and dequeuing packets for transmission in a communications network. The linecard has two paths: the receive path, which carries packets into the switch device from the network, and the transmit path, which carries packets from the switch to the network. In the receive path, received packets are processed and switched in an asynchronous, multi-stage pipeline utilizing programmable data structures for fast table lookup and linked list traversal. The pipelined switch operates on several packets in parallel while determining each packet's routing destination. Once that determination is made, each packet is modified to contain new routing information as well as additional header data to help speed it through the switch. Each packet is then buffered and enqueued for transmission over the switching fabric to the linecard attached to the proper destination port.Type: ApplicationFiled: October 31, 2005Publication date: March 9, 2006Inventors: Garry Epps, Michael Laor
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Publication number: 20060039374Abstract: A pipelined linecard architecture for receiving, modifying, switching, buffering, queuing and dequeuing packets for transmission in a communications network. The linecard has two paths: the receive path, which carries packets into the switch device from the network, and the transmit path, which carries packets from the switch to the network. In the receive path, received packets are processed and switched in a multi-stage pipeline utilizing programmable data structures for fast table lookup and linked list traversal. The pipelined switch operates on several packets in parallel while determining each packet's routing destination. Once that determination is made, each packet is modified to contain new routing information as well as additional header data to help speed it through the switch. Using bandwidth management techniques, each packet is then buffered and enqueued for transmission over the switching fabric to the linecard attached to the proper destination port.Type: ApplicationFiled: October 3, 2005Publication date: February 23, 2006Inventors: David Belz, Garry Epps, Michael Laor, Eyal Oren
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Publication number: 20050149651Abstract: A port adapter for connecting zero or more network interfaces to a host system having a SPI-4 bus is disclosed. The port adapter comprises zero or more network interfaces; a SPI-4 bus coupled to a host system to provide a communication channel between the host and the network interfaces; a control bus coupled to the host system for controlling and monitoring the port adapter; and interface logic that interfaces the SPI-4 bus and the control bus to the network interfaces. Methods are provided for selecting and using one of a small plurality of different packet formats for various networking technologies, so that the port adapter can hide details of the technology that it handles from the host system, and for operating the host system's SPI-4 bus at one of several speeds based on bandwidth requirements of the port adapter.Type: ApplicationFiled: October 6, 2003Publication date: July 7, 2005Inventors: David Doak, Garry Epps, Guy Fedorkow, Mark Gustlin, Steven Holmes, Randall Johnson, Promode Nedungadi, John Prokopik, Mohammed Tatar, Michael Taylor