Abstract: The system and method for clock synchronization, or calibration, for use in high speed asynchronous serial interfaces. The system and method is automatic, on-line, and occurs in real-time. The process of synchronization may also be started by a user. The calibration scheme is a form of adaptive filtering using 8B10B encoding. Once idle traffic is 8B10B encoded it becomes a stream of K28.5 characters. These characters are used to tune a clock frequency. The process stops, and two devices are synchronized, when the number of idle K28.5 traffic samples are uniformly approximately identical for any of two successive sample intervals.

Abstract: The system and method for clock synchronization, or calibration, for use in high speed asynchronous serial interfaces. The system and method is automatic, on-line, and occurs in real-time. The process of synchronization may also be started by a user. The calibration scheme is a form of adaptive filtering using 8B10B encoding. Once idle traffic is 8B10B encoded it becomes a stream of K28.5 characters. These characters are used to tune a clock frequency. The process stops, and two devices are synchronized, when the number of idle K28.5 traffic samples are uniformly approximately identical for any of two successive sample intervals.

Abstract: The novel credit-based adaptive flow control method and system for multi-stage, multi-dimensional, data switching architecture. The method and system of the present invention estimates and balances data flow in the switch architecture by using statistical information derived from the normal switching operation without requiring specific information from the previous stage. The multi-stage multi-dimensional switching architecture of the present invention includes three stages. The first and third stages are the buffering stages, and the second stage acts as a buffer-less crossbar switch node. Each stage includes an array of switching elements, and each element includes either a queuing processor or an arbitration processor arranged to progressively refine estimates of the data traffic from switch elements in the first stage by the second stage. The second stage maintains the statistic of valid traffic arrival and departure, and feedback grant information bit to the first stage.