Abstract: A method of forming a structure, an array of structures and a memory cell, the method of fabricating a structure, including: (a) forming a trench in a substrate; (b) depositing a first layer of polysilicon on a surface of the substrate, the first layer of polysilicon filling the trench; (c) chemical-mechanical-polishing the first layer of polysilicon at a first temperature to expose the surface of the substrate; (d) removing an upper portion of the first polysilicon from the trench; (e) depositing a second layer of polysilicon on the surface of the substrate, the second layer of polysilicon filling the trench; and (f) chemical-mechanical-polishing the second layer of polysilicon at a second temperature to expose the surface of the substrate, the second temperature different from the first temperature.

Abstract: A method of forming a structure, an array of structures and a memory cell, the method of fabricating a structure, including: (a) forming a trench in a substrate; (b) depositing a first layer of polysilicon on a surface of the substrate, the first layer of polysilicon filling the trench; (c) chemical-mechanical-polishing the first layer of polysilicon at a first temperature to expose the surface of the substrate; (d) removing an upper portion of the first polysilicon from the trench; (e) depositing a second layer of polysilicon on the surface of the substrate, the second layer of polysilicon filling the trench; and (f) chemical-mechanical-polishing the second layer of polysilicon at a second temperature to expose the surface of the substrate, the second temperature different from the first temperature.

Abstract: Disclosed is a process for forming a planarized multilevel ship wiring structure. Starting from a substrate having thereon at least a metal stud serving as vertical wiring between two levels of metallization, a quartz layer is deposited, obtaining a non-planar structure. A thick planarizing photoactive photoresist is applied. The photoresist is converted by silylation process into a silicate having substantially the same etch rate as that of quartz. Silylation is accomplished by, for example, subjecting to resist to a bath of hexamethyldisilazane, hexamethylcyclotrisilazane, octamethylcyclotetrasilazane, N,N,dimethylaminotrimethylsilane or N,N,diethylaminotrimethylsilane, for a period of time determined by the thickness of the resist. Unwanted portions of the silylated resist and quartz are etched back at 1:1 etch rate ratio to the level of the stud.

Abstract: Disclosed is a process for forming a planarized multilevel ship wiring structure. Starting from a substrate having thereon at least a metal stud serving as vertical wiring between two levels of metallization, a quartz layer is deposited, obtaining a non-planar structure. A thick planarizing photoactive photoresist is applied. The photoresist is converted by silylation process into a silicate having substantially the same etch rate as that of quartz. Silylation is accomplished by, for example, subjecting the resist to a bath of hexamethyldisilazane, hexamethylcyclotrisilazene, octamethylcyclotetrasilazane, N,N,dimethylaminotrimethylsilane or N,N,diethylaminotrimethylsilane, for a period of time determined by the thickness of the resist. Unwanted portions of the silylated resist and quartz are etched back at 1:1 etch rate ratio to the level of the stud.

Abstract: The planarization of structures having vertical interconnection studs embedded in an insulator layer utilizing a resist layer with dry etching in a CF.sub.4 ambient for equal etching of resist and the insulation to planarize the insulation, followed by dry etching in essentially a noble gas (argon) ambient for equal etching of the insulator layer and stud metal to desired planarization.