Abstract: An electromagnetic weld spatter removal device wherein a single control and power source may be utilized to fire multiple electromagnetic coils, thereby producing a cost savings. A first embodiment of the invention includes a contactor switch mechanism, a control mechanism, at least two contactors, and at least two electromagnetic coils for removing weld spatter. There is also disclosed a method for removing weld spatter using multiple electromagnetic coils for multiple welding stations. In a second embodiment there is disclosed a single enclosure housing the power supply, control logic board, at least two SCRs connected to at least two coils for the removal of weld spatter.

Abstract: An electromagnetic weld spatter removal device wherein a single control and power source may be utilized to fire multiple electromagnetic coils, thereby producing a cost savings. A first embodiment of the invention includes a contactor switch mechanism, a control mechanism, at least two contactors, and at least two electromagnetic coils for removing weld spatter.

Abstract: An integrated processor is fabricated on a single monolithic circuit and employs circuitry to accommodate data-intensive, view-intensive and voice-intensive requirements of modern-day PIDs. The integrated processor includes a CPU core, a memory controller, and a variety of peripheral devices to achieve versatility and high performance functionality. The integrated processor consumes less power by provision of a clock control unit including a plurality of phase-locked loops for generating clock signals of differing frequencies to appropriately clock the various subsystems of the integrated processor. The clock signals provided to the various subsystems by the clock control unit are derived from a single crystal oscillator input signal. A power management unit is incorporated within the integrated processor to control the frequency and/or application of certain clock signals to the various subsystems, as well as to control other power management related functions.

Abstract: An integrated processor is fabricated on a single monolithic circuit and employs circuitry to accommodate data-intensive, view-intensive and voice-intensive requirements of modern-day PIDs. The integrated processor includes a CPU core, a memory controller, and a variety of peripheral devices to achieve versatility and high performance functionality. The integrated processor consumes less power by provision of a clock control unit including a plurality of phase-locked loops for generating clock signals of differing frequencies to appropriately clock the various subsystems of the integrated processor. The clock signals provided to the various subsystems by the clock control unit are derived from a single crystal oscillator input signal. A power management unit is incorporated within the integrated processor to control the frequency and/or application of certain clock signals to the various subsystems, as well as to control other power management related functions.

Abstract: The present invention provides a means for operating the CPU in a single chip microprocessor at a multipe of the cycle speed of the memory bus. With the present invention, first and second timing signals are provided. The frequency of the second timing signal is a multiple of the frequency of the first timing signal. The second or fast timing signal is provided to the CPU and the first or slower timing signal is provided to the memory subsystem. A bus interface unit is interposed between the CPU and the memory bus. This bus interface unit receives the RDY signal (i.e. the ready signal) from the memory subsystem and modifies it before it is provided to the CPU. The "ready" signal from the memory subsystem is in an undefined state for a significant portion of each bus cycle. Since at least two CPU cycles occur during each memory access, the bus interface unit must ensure that the CPU does not misinterpret the ready signal from the memory subsystem. The bus interface unit also must modify the ADS signal (i.e.

Abstract: The present invention provides a means for operating the CPU in a single chip microprocessor at a multipe of the cycle speed of the memory bus. With the present invention, first and second timing signals are provided. The frequency of the second timing signal is a multiple of the frequency of the first timing signal. The second or fast timing signal is provided to the CPU and the first or slower timing signal is provided to the memory subsystem. A bus interface unit is interposed between the CPU and the memory bus. This bus interface unit receives the RDY signal (i.e. the ready signal) from the memory subsystem and modifies it before it is provided to the CPU. The "ready" signal from the memory subsystem is in an undefined state for a significant portion of each bus cycle. Since at least two CPU cycles occur during each memory access, the bus interface unit must ensure that the CPU does not misinterpret the ready signal from the memory subsystem. The bus interface unit also must modify the ADS signal (i.e.

Abstract: A product press formed from a paperboard and a method for forming the same is provided, wherein the product includes a press formed three-dimensional curvilinear region having a desired shape and containing a formation improvement structure for facilitating the press formation and maintenance of the desired product shape and for preventing the machine directionality of the paperboard from distorting the product from its desired shape. The press formed paperboard product of the preferred embodiment comprises a planar wall having a periphery which is at least partially curvilinear and a peripheral wall angularly oriented with respect to the planar wall. The peripheral wall extends along at least a portion of the curvilinear periphery of the planar wall and the closest portion of the peripheral wall is spaced a substantial radial distance from the periphery of the planar wall.

Abstract: Apparatus for measuring fiber orientation anisotropy in a web of fibrous material includes a microwave generator, a waveguide through which a microwave signal is propagated axially and in which an electric field is established in one direction perpendicular to the waveguide axis, the waveguide having a gripping means which provides a gripping means for specimen insertion, a detector for measuring intensity of the microwave signal propagated through the waveguide and a metering means for numerically evaluating the intensity of the propagated signal. The intensity of the propagated signal is measured (1) with the waveguide empty, (2) with the specimen inserted in the waveguide in a plane normal to the axis and with its machine direction aligned with the electric field and (3) with the specimen inserted in the waveguide in the normal plane and with its cross direction aligned with the direction of the electric field.

Abstract: A device which measures the velocity of ultrasonic waves in a moving web is provided. A pair of wheels is mounted for continuous surface contact with the paper and a transducer, which contacts the web on each revolution, is located in each wheel for relating electrical and mechanical signals. Timing means measures the time it takes a mechanical signal generated at the first wheel to reach the second wheel. Noise reducing and amplifying means are provided for effective operation.