Patents by Inventor Gary A. Browning

Gary A. Browning has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9209792
    Abstract: The present invention systems and methods enable configuration of functional components in integrated circuits. In one embodiment clock signal selection system includes an arbitration component, a control component, and a selection component The arbitration component coordinates arbitration eligibility between a plurality of clock signals. The control component controls the coordination utilizing a clock signal from the plurality of clock signals. The selection component selects between the plurality of signals.
    Type: Grant
    Filed: August 15, 2007
    Date of Patent: December 8, 2015
    Assignee: NVIDIA CORPORATION
    Inventor: Gary A. Browning
  • Publication number: 20020191283
    Abstract: A light transmission projection screen including a transparent lens sheet, a plurality of longitudinal spaced apart grooves provided in a front surface of the lens sheet, a plurality of flat portions in the front surface of the lens sheet between the plurality of spaced apart grooves, a transparent optical layer provided on an inner surface of each of the V grooves, an optically opaque material filling only the grooves and a diffusion layer provided on the front surface of the lens sheet covering the flat portions and grooves.
    Type: Application
    Filed: June 14, 2001
    Publication date: December 19, 2002
    Inventor: Gary A. Browning
  • Patent number: 5420997
    Abstract: A random access memory (RAM) complex that can concurrently read and write to different addresses. The memory complex includes two RAMs, each having an address selector, includes a data out multiplexer for selecting outputs from one of the RAM's. A tag array stores an array of tag, one for each address in the RAM's. The tag marks which one of the two RAM's has the valid data for the corresponding read address. During a concurrent read and write cycle, the tag selects the read address for one RAM, selects the write address for the other RAM and a staged copy of the tag controls the multiplexer to select data from the correct RAM for the data out.
    Type: Grant
    Filed: January 2, 1992
    Date of Patent: May 30, 1995
    Inventors: Gary A. Browning, Allan J. Zmyslowski, Edward G. Ryba