Abstract: A magnetic memory array with an improved word line configuration is provided. In some embodiments, the magnetic memory array may be adapted to selectively supply voltage from a single source line to one or more transistors arranged within a first row of the magnetic memory array and to one or more transistors arranged within a second row of the magnetic memory array. In addition or alternatively, the magnetic memory array may be configured to enable current flow along a single current path through a magnetic junction and along multiple paths extending from the single current path to a plurality of transistors. In some embodiments, the plurality of transistors may be formed from a contiguous conductive structure comprising the word line. In some cases, the word line may be configured to include at least two transistors that share a common diffusion region.

Abstract: A memory storage circuit is provided which includes a plurality of magnetic elements each configured to store bits in a first or a second logic state. The storage circuit may further include a plurality of transistors coupled to at least two of the magnetic elements. Such a plurality of transistors may be collectively configured to store bits in the first and second logic states as well. The memory storage circuit may include circuitry configured to load bits from a set of the magnetic elements into the plurality of transistors. Another circuit is provided which includes a magnetic element interposed between a bit line and an electrode. The circuit may further include a first set of circuitry configured to induce current flow through the magnetic element in a direction from the electrode to the bit line. A method for operating a memory storage circuit with the aforementioned configurations is also provided.

Abstract: A memory array configuration is provided that includes a plurality of magnetic cell junctions and a conductive line comprising a gate of a first transistor configured to enable a read operation for one of a plurality of magnetic cell junctions and a gate of a second transistor configured to enable a write operation for another of the plurality of magnetic cell junctions. Another memory array configuration is provided which includes a set of conductive structures serially coupled to a bit line spaced apart from and, in some embodiments, directly above a magnetic cell junction, a transistor coupled to the set of conductive structures and a program line collectively configured with the bit line to induce current flow through the set of conductive structures upon an application of a voltage to a gate of the transistor. A method for operating such a magnetic memory array is also contemplated herein.

Abstract: A memory circuit which is adapted to identify memory cells within a first time interval for a write operation of the circuit and identify the memory cells within a second time interval for a read operation of the circuit is provided. In some cases, the memory circuit may include an address path which includes a different circuit path for the read operations than for the write operations of the circuit. In addition, the memory circuit may include a means for intentionally delaying the identification of the memory cells for the write operation of the circuit. In some cases, the memory circuit may further include a means for intentionally delaying the identification of memory cells for the read operation of the circuit. Alternatively, the memory circuit may be absent a means for intentionally delaying the identification of memory cells for the read operation of the circuit.

Abstract: A method for utilizing a delay lock loop to cover a wide delay range. In one method embodiment, the present invention receives a reference clock pulse. Next, in a first loop, a phase variation is adjusted between the feedback clock pulse and the reference clock pulse utilizing a coarse delay in conjunction with a first fine delay. The resulting pulse is then output to a chip delay and then sent back to the delay lock loop as a feedback clock pulse. Additionally, in a second loop, the phase variation is adjusted between said second loop and said first loop utilizing the coarse delay in conjunction with a second fine delay, wherein the second fine delay has a delay range for adjusting the phase variation which overlaps the delay range of the first fine delay of the first loop.

Abstract: An integrated circuit device includes an input circuit; logic circuitry coupled to the input circuit; an output circuit coupled to the logic circuitry; and a select circuit coupled to the input circuit, output circuit and logic circuitry. The select circuit generates a select signal that causes the input circuit, output circuit and logic circuit to operate according to a first state or a second state. The output buffer is configured to receive the select signal which selects output buffer operation at the first state or the second state. The output buffer is also configured to maintain a constant slew rate while operating in either the first or second state.

Abstract: A system and method are disclosed herein for leakage testing of a static random access memory (SRAM) semiconductor memory device. Subtle leakage defects may be present in some devices in the early stages of SRAM production. These defects may later result in hard failures when packaged devices are burned in, but are not detected by functional tests performed during wafer sort. The leakage defects are associated with complementary bit line pairs within the SRAM matrix, and may be revealed by leakage current measurements made between all of the complementary bit line pairs within the SRAM. Comparatively minor modifications to the internal circuitry of the SRAM enable the leakage measurements to be performed during wafer sort, so defective devices can be screened out prior to packaging, lead-bonding, etc.

Abstract: An apparatus comprising a first circuit, a second circuit, and an output circuit. The first circuit may be configured to generate a first digital output in response to (i) a reference input and (ii) a feedback input. The second circuit may be configured to generate a second digital output in response to (i) the first digital output and (ii) a second feedback input. The output circuit may be configured to generate a third output in response to a data input, wherein an output impedance of the output circuit is adjusted in response to (i) the first digital output and (ii) the second digital output.

Abstract: An integrated circuit device includes an input circuit; logic circuitry coupled to the input circuit; an output circuit coupled to the logic circuitry; and a select circuit coupled to the input circuit, output circuit and logic circuitry. The select circuit generates a select signal that causes the input circuit, output circuit and logic circuit to operate according to a first state or a second state. The output buffer is configured to receive the select signal which selects output buffer operation at the first state or the second state. The output buffer is also configured to maintain a constant slew rate while operating in either the first or second state.

Abstract: A self-resetting logic stage provides for a relatively faster propagation of pulse signals and for relatively less power consumption. For a self-resetting logic stage in a digital logic path of successive logic stages, a forward path creates the forward edge for an output pulse signal and a reset path creates a reset or trailing edge for the output pulse signal. The propagation delay for the reset path may be increased for successive stages in the logic path to minimize or avoid overlap current. As the increased propagation delay increases the width of a pulse signal as the pulse signal propagates from stage to stage, logic stages in the logic path may be configured to reduce the width of the pulse signal, for example when the pulse signal approaches a width that may limit the cycle time for the logic path. Logic stages in the logic path may also be configured to provide for relatively quicker reset recovery to minimize any increase in cycle time.

Abstract: A Bi-CMOS ECL semiconductor memory cell having a read word line, a write word line and a read bit line is disclosed. The cell includes a bistable circuit having complimentary outputs and also includes a first transfer device and a second transfer device, each having a gate electrode and a current path, the gate electrode of one transfer device being coupled to one of the complimentary outputs of the bistable circuit and the gate of the other transfer device being coupled to the other complimentary output, and the two current paths of the two transfer devices being coupled in series between the read word line and a first reference voltage. The cell further includes a bipolar transistor device having a base, a collector and an emitter.

Abstract: An analog to digital converter for converting an analog input voltage into a four most significant bit group and a four least significant bit group of digital outputs at a first and a second group of output terminals. The complete analog to digital converter includes a first analog to digital converter for converting the analog input voltage into a four most significant bit group of digital outputs at the first group of output terminals. A digital to analog converter which is coupled to the first group of output terminals converts the four most significant bit group of digital outputs into a first analog current which is proportional to the magnitude of the four most significant bit group of digital outputs and into a second analog current such that the sum of the first and the second analog currents is a constant.