Abstract: A synchronization technique in which the frame used for synchronization is different from that used for normal data communiction and contains few if any bits other than those used to establish synchronization. At the beginning of data communication, the synchronization frame is stored in one of a pair of memories and this frame is read out of the memory onto a communication channel between the local and remote stations. At the same time, the other memory is used to store the frame that is normally used for data communication. When synchronization is established between the local and remote stations, signal generation shifts from the first memory to the second; and the second memory immediately begins to produce the channel select and overhead signals needed for data communication. Illustratively, the synchronization frame contains less than one hundred bits and in a preferred embodiment a total of forty-eight bits are used for synchronization.

Abstract: A method and apparatus are described for ensuring that control signals from every data channel are transmitted periodically regardless of any change in these control signals. The apparatus comprises a counter for counting the number of control signals transmitted, decision logic for determining when it is time to transmit a set of control signals regardless of any change in these signals and circuitry for selecting the channel whose signals are to be transmitted. The apparatus provides additional equipment for determining when the control signals for a particular channel have changed and for transmitting such signals with suitable error checking. The apparatus also provides equipment for interleaving the two flows of control signals without loss of the control signals which are changed.

Abstract: A method and apparatus are described in which the control signals for a data channel are transmitted along with the channel aaddress. The control signal and its address are transmitted on a bit interleaved basis in response to CONTROL select signals that are generated as part of the frame. In accordance with the invention, the CONTROL select signals are distributed relatively uniformly throughout the frame. At the receiver, the bits of the control signal and its address are reassembled and the address is used to route the control signal to its proper channel. Further, the bandwidth assigned to control signaling is increased by inserting CONTROL select signals in all time slots that are available in the frame after the necessary channel select signals and other overhead select signals have been assigned. This technique is particularly advantageous in a system having a fixed aggregate transmission bandwidth, variable loads and the capability of automatically reconfiguring the frame.

Abstract: A clock rate generator is described which can be programmed to provide an output clock rate that is N/M times the rate of a standard clock where N and M are integers. The generator comprises a counter, a programmable memory, reset logic and a clocking control. A standard clock is applied to the counter so that the counter is advanced by one for each clock bit. The output of the counter is connected to the input lines of the programmable memory where a pattern of binary ones and zeros are stored. The output of the programmable memory is applied to the clocking control to combine successive bits of the same polarity. The divisor M is determined by the number of standard clock counts between successive resets of the counter. The multiplier N is determined by the number of output cycles from the clocking control between successive resets of the counter.