Abstract: A sequence controller includes a plurality of time slice modules, each producing an adjustable number of sequentially asserted time slice signals, and a plurality of phase generators each having as input the time slice signals produced by an associated one of the time slice modules. Each phase generator produces a square wave output signal, the timing of the rising and trailing edges of each pulse thereof being determined by a selectable pair of its input time slice signals. A state machine monitors time slice signals produced by the time slice modules and transmits a separate enable signal to each time slice generator in response to the time slice signals. Each of the time slice modules produces time slice signals only when output enabled by an enable signal from the state machine.