Abstract: Aspects of the invention may include a dual port Ethernet controller having a bus interface, a first Ethernet controller coupled to the bus interface such as a PCI bus interface and a second Ethernet controller coupled to the bus interface. The first Ethernet controller, second Ethernet controller and bus interface are integrated within a single chip. The dual port Ethernet controller may also include an arbiter, which is coupled to the first Ethernet controller, the second Ethernet controller and the bus interface. A plurality of shared resources may be coupled to one or more of the first Ethernet controller, the second Ethernet controller and the arbiter. The shared resources may include, but is not limited to, a non-volatile memory 304 and a general purpose input/out interface.

Abstract: A method for processing network data is disclosed and may include receiving data via a single bus interface to which each of a plurality of Ethernet controllers are coupled, where the Ethernet controllers are integrated within a single chip. A particular one of the integrated Ethernet controllers may be identified based on information within the received data. The particular one of the integrated Ethernet controllers may be granted access to a shared resource within the single chip. The access to the shared resource may be granted using at least one semaphore register within the shared resource. The particular one of the integrated Ethernet controllers may be granted access to the single bus interface. The information may include a bus identifier, a bus device identifier and/or a bus function identifier. The shared resource may include a nonvolatile memory (NVM).

Abstract: A method for processing network data is disclosed and may include receiving data via a single bus interface to which each of a plurality of Ethernet controllers are coupled, where the Ethernet controllers are integrated within a single chip. A particular one of the integrated Ethernet controllers may be identified based on information within the received data. The particular one of the integrated Ethernet controllers may be granted access to a shared resource within the single chip. The access to the shared resource may be granted using at least one semaphore register within the shared resource. The particular one of the integrated Ethernet controllers may be granted access to the single bus interface. The information may include a bus identifier, a bus device identifier and/or a bus function identifier. The shared resource may include a nonvolatile memory (NVM).

Abstract: A system for arbitrating access to a shared resource is disclosed and may include a bus interface, a first network controller for handling a first host function associated with a first host process, a second network controller for handling a second host function associated with a second host process, and an arbitrator for granting access to the shared resource for one of the first host process and the second host process. The arbitrator may facilitate a transfer of information to and from the bus interface and the shared resource. The first network controller and the second network controller may be integrated within a single chip. The shared resource may be a nonvolatile memory, flash memory interface, an EEPROM interface, and/or a Serial Programming Interface (SPI).

Abstract: Certain embodiments of the invention may include receiving at least one message via a single bus interface to which each integrated Ethernet controller may be coupled. A bus identifier, bus device identifier and bus function identifier corresponding to the received message and which identifies a particular one of the integrated Ethernet controllers may be determined. The received message may be transferred to the particular integrated Ethernet controller based on the determined bus identifier, bus device identifier and bus function identifier, which were previously generated. The method may further include associating a bus function with the particular integrated Ethernet controller and mapping the associated bus function identifier to the bus function. A bus function process may be associated with the particular integrated Ethernet controller. The bus identifier may be associated with the single bus interface and the device identifier may be associated with the plurality of integrated Ethernet controllers.

Abstract: A predictive time base generator having predictive synchronizer and replica delay element coupled with the synchronizer feedback delay loop. The predictive time base generator receives a clock signal delayed by a predetermined clock delay and produces a predictive time signal advanced in time by an amount represented by the replica delay element. The replica delay element can replicate one or both of a predetermined clock delay and a predetermined data delay, substantially nullifying the respective delays in critical signal paths of a device. The replica delay element can include replicas of structure(s) found in an incoming clock path and an outgoing data path, such elements including, for example, voltage level shifters, buffers or data latches, multiplexers, wire element models, and the like. A predictive computer bus interface adapter which incorporates the aforementioned predictive time base generator also is provided.

Abstract: A predictive time base generator having predictive synchronizer and replica delay element coupled with the synchronizer feedback delay loop. The predictive time base generator receives a clock signal delayed by a predetermined clock delay and produces a predictive time signal advanced in time by an amount represented by the replica delay element. The replica delay element can replicate one or both of a predetermined clock delay and a predetermined data delay, substantially nullifying the respective delays in critical signal paths of a device. The replica delay element can include replicas of structure(s) found in an incoming clock path and an outgoing data path, such elements including, for example, voltage level shifters, buffers or data latches, multiplexers, wire element models, and the like. A predictive computer bus interface adapter which incorporates the aforementioned predictive time base generator also is provided.

Abstract: Aspects of the invention may include a dual port Ethernet controller having a bus interface, a first Ethernet controller coupled to the bus interface such as a PCI bus interface and a second Ethernet controller coupled to the bus interface. The first Ethernet controller, second Ethernet controller and bus interface are integrated within a single chip. The dual port Ethernet controller may also include an arbiter, which is coupled to the first Ethernet controller, the second Ethernet controller and the bus interface. A plurality of shared resources may be coupled to one or more of the first Ethernet controller, the second Ethernet controller and the arbiter. The shared resources may include, but is not limited to, a non-volatile memory 304 and a general purpose input/out interface.

Abstract: Certain embodiments of the invention may include receiving at least one message via a single bus interface to which each integrated Ethernet controller may be coupled. A bus identifier, bus device identifier and bus function identifier corresponding to the received message and which identifies a particular one of the integrated Ethernet controllers may be determined. The received message may be transferred to the particular integrated Ethernet controller based on the determined bus identifier, bus device identifier and bus function identifier, which were previously generated. The method may further include associating a bus function with the particular integrated Ethernet controller and mapping the associated bus function identifier to the bus function. A bus function process may be associated with the particular integrated Ethernet controller. The bus identifier may be associated with the single bus interface and the device identifier may be associated with the plurality of integrated Ethernet controllers.

Abstract: A predictive time base generator having predictive synchronizer and replica delay element coupled with the synchronizer feedback delay loop. The predictive time base generator receives a clock signal delayed by a predetermined clock delay and produces a predictive time signal advanced in time by an amount represented by the replica delay element. The replica delay element can replicate one or both of a predetermined clock delay and a predetermined data delay, substantially nullifying the respective delays in critical signal paths of a device. The replica delay element can include replicas of structure(s) found in an incoming clock path and an outgoing data path, such elements including, for example, voltage level shifters, buffers or data latches, multiplexers, wire element models, and the like. A predictive computer bus interface adapter which incorporates the aforementioned predictive time base generator also is provided.

Abstract: A predictive time base generator having predictive synchronizer and replica delay element coupled with the synchronizer feedback delay loop. The predictive time base generator receives a clock signal delayed by a predetermined clock delay and produces a predictive time signal advanced in time by an amount represented by the replica delay element. The replica delay element can replicate one or both of a predetermined clock delay and a predetermined data delay, substantially nullifying the respective delays in critical signal paths of a device. The replica delay element can include replicas of structure(s) found in an incoming clock path and an outgoing data path, such elements including, for example, voltage level shifters, buffers or data latches, multiplexers, wire element models, and the like. A predictive computer bus interface adapter which incorporates the aforementioned predictive time base generator also is provided.

Abstract: A network transmitter device and network receiver device is described. The network transmitter device transmits a first voltage potential, a second voltage potential, a third voltage potential and a fourth voltage potential over a first pair of output lines and a second pair of output lines in response to digital signals received over a data input. The network receiver device receives network signals of a first voltage potential, a second voltage potential, a third voltage potential, a fourth voltage potential and a fifth voltage potential over a first pair of output lines and a second pair of output lines. The network receiver device transmits digital signals corresponding to the network signals.

Abstract: A method and apparatus for automatically resolving I/O address conflicts among hardware adapters coupled to a common bus in a computer system. System I/O software tests each address space of a set of possible automatic conflict resolution (ACR) adapter address spaces for bus conflicts between the ACR adapters and non ACR adapters. For each address space having a conflict, the system I/O software shifts the address spaces of the ACR adapters to a next sequential address space of the set of possible address spaces. Thereafter, the system I/O software reallocates the address space of each ACR adapter, such that the address spaces of the ACR adapters do not overlap, and are not in conflict with the non ACR adapters.