Abstract: Data management systems, such as used in disk control units, employ memory entry lists to help keep track of user data. Improved performance of entry list maintenance is provided by the present invention. Much of the protocol employed to conduct such maintenance is preferably performed by hardware-based logic, thereby freeing other system resources to execute other processes. New entries to the memory list are only allowed at predetermined addresses and entries are updated by writing a predetermined data pattern to a previously allocated address. Optionally, improved error detection, such as a longitudinal redundancy check, may also be performed in an efficient manner during entry list maintenance to assure the integrity of the list.

Abstract: A method of verifying the passage of a data write across a bus is provided including sending the data write from an originator across the bus to a target, counting the number of data entries received at the target with a counter, and transmitting a return echo write from the target across the bus to a return address. The method further includes attaching the counter value to other data associated with the return echo write and polling the return address. The method allows determination of the completion of a data write by comparing the number of data entries included in the data write with the counter value polled from the return address. Alternatively, in a data streaming environment the progress of a data write may be determined by comparing the number of data entries included in the data write at a select point in time with the counter value polled from the return address. Typical data entries which are counted may include, but are not limited to, bytes, words, double words, or similar data quantities.

Abstract: A connection is provided between logical macros to allow prioritization of operations in accordance with an arbitration scheme that distinguishes between operations based on such factors as priority or size of transaction. The invention allows connection of logical macros and prioritizes the appropriate operation for the resources available to optimize data throughput to optimize the utilization of multiple buses. A first arbiter manages data transmissions over a first communication bus. Arriving short or high-priority messages are transmitted over a second communication bus managed by a second arbiter, but only if the target logical macro is not the same as currently targeted by the first arbiter.

Abstract: A method to convert a plurality of sectors from a first sector format to a second sector format is disclosed. The method provides (N) contiguous first sectors comprising a first sector format to a sector format conversion device which includes a buffer and a data queue, where those (N) first sectors comprise a first number of bytes, and determines that (M) contiguous second sectors, comprising a second sector format, comprise at least the first number of bytes. The method overlays the (i)th first sector onto part or all of the (j)th second sector, and enqueues the newly-overlain (j)th second sector. The method then transmits the newly-overlain (j)th second sector to a data storage device, and writes that (j)th overlain second sector to an information storage medium.

Abstract: A method is disclosed to preserve data integrity during loss of power to an information storage and retrieval system. Applicants' method converts a plurality of sectors having a first sector format to a plurality of sectors having a second sector format. If a power failure warning is received during the sector format conversion process, the method prefetches the next second sector, overlays the next first sector onto part of all of that prefetched second sector, and saves the newly-written second sector before loss of utility power. After restoration of utility power to the information storage and retrieval system, Applicants' method writes that newly-written second sector to an information storage medium.

Abstract: A trace information queueing system receives a plurality of trace information signals and transmits them through a common connector. The multiple trace information signals may be multiplexed. Each edge of a clock signal may be used to enable transmission of different trace information signals. Alternatively, separate clocks signals may be provided for each trace information signal. A programmable logic device may be used to both multiplex the trace information signals and produce the clock signals necessary to enable their transmission.

Abstract: A back-up power source and a back-up storage device are utilized to power a processor and a volatile memory device during a primary power failure. An emergency data-storage algorithm is invoked to create a table of modified data analogous to data residing in a non-volatile memory device associated with a different processor. This table of modified data is written to the back-up storage device.

Abstract: An apparatus for limiting volatile computer memory based on available energy in an auxiliary power source comprises an energy monitor module configured to determine an amount of available energy in the auxiliary power source. Also provided is a memory status module configured to determine an amount of volatile computer memory allocated for use in a computer and a memory adjustment module configured to adjust the amount of volatile computer memory allocated for use in the computer based on the amount of available energy in the auxiliary power source.