Abstract: Data transfers between a workstation bus and a graphics adapter bus are handled by a plurality of first-in-first-out (FIFO) buffers, each of which is independently operable to transfer data in a selected direction between the two buses. The FIFOs are accessible either directly by the workstation processor or by means of a DMA operation. Each FIFO is assigned a unique range of addresses in the address space of the workstation processor to permit a workstation process to transfer a block of data to or from a selected FIFO using a single instruction. Workstation writes (reads) to a FIFO are suspended in response to a first status signal indicating that the high (low) threshold for that FIFO has been reached and are restarted in response to a second status signal indicating that the low (high) threshold has been reached.

Abstract: A plurality of processors or intelligent controllers separately utilize discrete pages of a large memory. Within each of these pages a processor can address a plurality of subdivisions or blocks utilizing the processors' address lines. Thus, separate processors having access to this memory and having a limited addressing capability can utilize a plurality of different pages of this memory, within an identical address range, and nevertheless remain confined to separate memory environments established for each of the separate processors. This is accomplished by use of a hardware register to point the separate processors to their assigned pages of the memory and a stored translate table to point to particular blocks of memory within the pages in accordance with a portion of an address generated by the processor accessing the memory.

Abstract: A privacy wall for joining a floor and ceiling, which wall includes a lower panel projecting upwardly from the floor, and a privacy panel extending vertically between the ceiling and the upper edge of the lower panel. The privacy panel has upper and lower edges supported within retainers confined within recesses defined by support tracks. The upper and lower retainers are identical but reversely vertically oriented relative to the respective recesses. Each retainer includes a central base wall and pairs of first and second legs projecting outwardly in opposite directions to define first and second oppositely oriented channels which accommodate the edge of the privacy panel therein. The first legs are short and inclined inwardly so that the lower edge of the panel can be sealingly accommodated therebetween. The second legs are of greater length and have sideward flanges adjacent the ends thereof.