Abstract: A reading aid for mounting to the underside of a horizontal surface, such as a cabinet or a shelf, includes a mounting member, an optical magnification device, an illumination source, a switch and a power source. The mounting member is mounted to the underside of the horizontal surface and the optical magnification device is pivotally attached to the mounting member. The optical magnification device is moveable between a storage position and an operative position. The illumination source, the power source and the switch are connected in circuit for illuminating any reading material situated beneath the reading aid.

Abstract: A heat sink is disclosed for directing heat away from an electronic component dissipating heat. The heat sink includes a thermally conductive base formed of a variable density graphite foam article. This graphite foam heat sink having variable foam densities provides for higher cooling capacity than existing heat sinks.

Abstract: An automatic clock calibration circuit includes a source of clock signals and an equal number of corresponding clock reference signals. Corresponding delay elements are connected between the source and the load driven by each of the clock signals. A phase frequency detector detects the phase differences between each clock signal, at the point at which it is applied to its load, and its corresponding clock reference signal. A microcontroller adjusts the delay of the delay elements according to the detected phase differences.

Abstract: A delay chain having a known number of delay elements providing various delayed outputs of its input, a first and a second register set, and preferably, an array of multiplexors, are provided to measure the frequency of a digital signal, and the high and low time of its period. The digital signal to be measured is provided to the delay chain as input. A first and a second sample of the various delayed outputs are taken at the beginning and the end of a known time period, and stored in the first and second registers, one delayed output per register bit. The sample results stored in the register sets are read out through the multiplexors, and used to determine the frequency of the digital signal being measured, and the high and low time of its period.

Abstract: A first and a second input generating circuits, a first and a second set of counters, and a first and a second comparison circuits are provided to test whether the frequencies of a first and a second periodic digital signal are symmetric. The first and second input generating circuits generate enable inputs for the first and second sets of counters using the first and second digital signals respectively. The first and second sets of counters count the first and second digital signals while the enable inputs are provided. The first comparison circuit monitors the first set of counters, and stops both input generating circuits from providing further enable inputs to both sets of counters, after the first set of counters reaches a predetermined level, thereby stopping both sets of counters from further counting.

Abstract: The invention is for improving the performance of a microprocessor system by reducing the skew between the system clock and critical control signals. Reduction in this skew reduces or eliminates the need for waitstates on data accesses to random access memory devices thereby improving system performance. A clock PAL is programmed to function as an asynchronous state machine to generate the clock signals and the memory device chip select. A clock source from an oscillator is input to the PAL. This clock source is buffered by the PAL and presented at the PAL outputs as the system clock. The memory device chip select is also generated inside this PAL using the source clock and other signals generated inside the PAL.

Abstract: Each of the remote high speed circuits of a digital system is provided with a sync pulse generation circuit for generating periodic sync pulses with a predetermined periodicity using a control value. Additionally, each of the remote high speed circuits is further provided with a sampling circuit for sampling the sync pulse generation control value, a comparison circuit for determining whether each of the sampled sync pulse generation control values are consistent, and an adjustment circuit for adjusting the sync pulse generation control value of the particular remote high speed circuit. Furthermore, a sync pulse generation coordinator comprising a clock selection circuit, a delay line, a delayed clock selection circuit, and a coordination pulse generation circuit is provided to the digital system for generating periodic coordination pulses. The periodic coordination pulses are used to control the sampling and comparison.

Abstract: An address converter that reduces the number of address bit changes between successive sequential addresses is provided to a RAM address bus for a sequentially accessed RAM. In the presently preferred embodiment, the address converter comprises a plurality of XOR gates for converting the access addresses into gray coded access addresses having at most one address bit change between successive access addresses. As a result, the power consumed and the noise generated over the address bus is reduced, thereby conserving power available and minimizing device package pins required by the digital system having the RAM and the RAM address bus.

Abstract: Each data sending high speed circuit generating and sending a stream of data slices and a stream of clock pulses is provided with a sync pulse generation circuit for synchronously generating and sending an accompanying stream of periodic sync pulses. The various streams of data slices, clock pulses, and periodic sync pulses incur varying amount of delays as they travel from the data sending high speed circuits to a data acquisition circuit. The data acquisition high speed circuit is provided with a plurality of circular buffer chains of appropriate length for independently buffering the skewed data slices until all corresponding data slices have been received and buffered, and then concurrently reading the buffered corresponding data slices out of the circular buffer chains.

Abstract: A digital clock reconstruction circuit comprising a first flip flop, a programmable delay chain, and a first assembly of gates is provided to digitally compensate an entering digital clock's skew for a high speed digital circuit by digitally reconstructing the entering clock. The reconstructed clock will also provide the minimum amount of high and low time in a period required by the components of the high speed circuit. Additionally, at least one measurement or comparison circuit is provided for measuring the frequencies of the reconstructed clock under various delay settings of the programmable delay chain to calibrate the digital clock reconstruction circuit. Under the calibration process of the present invention, the delay setting is determined iteratively, starting from an initial setting and varying the delay setting in a predetermined manner.