Patents by Inventor Gary Brian Wallichs
Gary Brian Wallichs has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240004810Abstract: A system including a host device and an integrated circuit. The host device includes a host memory, the host memory storing configuration data. The integrated circuit device includes an integrated circuit and a direct memory access circuitry. The direct memory access circuitry pulls the configuration data from the host memory. The direct memory access circuitry also programs the integrated circuit based on the configuration data.Type: ApplicationFiled: July 1, 2022Publication date: January 4, 2024Inventors: Gary Brian Wallichs, Andrew Martyn Draper, Kye Howe Wong, Kalen Brunham, Jeffrey Edward Erickson
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Publication number: 20230305982Abstract: An interface bridge to enable communication between a first integrated circuit die and a second integrated circuit die is disclosed. The two integrated circuit die may be connected via chip-to-chip interconnects. The first integrated circuit die may include programmable logic fabric. The second integrated circuit die may support the first integrated circuit die. The first integrated circuit die and the secondary integrated circuit die may communicate with one another via the chip-to-chip interconnects using an interface bridge. The first and second component integrated circuits may include circuitry to implement the interface bridge, which may provide source-synchronous communication using a data receive clock from the second integrated circuit die to the first integrated circuit die.Type: ApplicationFiled: May 31, 2023Publication date: September 28, 2023Inventors: Jeffrey Erik Schulz, David W. Mendel, Dinesh D. Patil, Gary Brian Wallichs, Keith Duwel, Jakob Raymond Jones
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Publication number: 20230289319Abstract: Systems and methods are provided for supporting wide-protocol interface across a multi-die interconnect interface. Data signals of a wide-protocol interface are split into a plurality of data streams. A handshake signal is established between a first circuit and a second circuit, whereby the first circuit and second circuit are dies of a multi-die device. The first circuit transmits the plurality of data streams to the second circuit via a plurality of multi-die interconnect channels. Each data stream of the plurality of data streams are compressed based on the handshake signal in order to provide wide-protocol interface with reduced number of required pins.Type: ApplicationFiled: April 12, 2023Publication date: September 14, 2023Inventors: Gary Brian Wallichs, Keith Duwel, Cora Lynn Mau
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Patent number: 11693810Abstract: An interface bridge to enable communication between a first integrated circuit die and a second integrated circuit die is disclosed. The two integrated circuit die may be connected via chip-to-chip interconnects. The first integrated circuit die may include programmable logic fabric. The second integrated circuit die may support the first integrated circuit die. The first integrated circuit die and the secondary integrated circuit die may communicate with one another via the chip-to-chip interconnects using an interface bridge. The first and second component integrated circuits may include circuitry to implement the interface bridge, which may provide source-synchronous communication using a data receive clock from the second integrated circuit die to the first integrated circuit die.Type: GrantFiled: December 24, 2021Date of Patent: July 4, 2023Assignee: Intel CorporationInventors: Jeffrey Erik Schulz, David W. Mendel, Dinesh D. Patil, Gary Brian Wallichs, Keith Duwel, Jakob Raymond Jones
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Patent number: 11657016Abstract: Systems and methods are provided for supporting wide-protocol interface across a multi-die interconnect interface. Data signals of a wide-protocol interface are split into a plurality of data streams. A handshake signal is established between a first circuit and a second circuit, whereby the first circuit and second circuit are dies of a multi-die device. The first circuit transmits the plurality of data streams to the second circuit via a plurality of multi-die interconnect channels. Each data stream of the plurality of data streams are compressed based on the handshake signal in order to provide wide-protocol interface with reduced number of required pins.Type: GrantFiled: November 9, 2021Date of Patent: May 23, 2023Assignee: Altera CorporationInventors: Gary Brian Wallichs, Keith Duwel, Cora Lynn Mau
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Publication number: 20220197855Abstract: Systems and methods described herein may relate to data transactions involving a microsector architecture. Control circuitry may organize transactions to and from the microsector architecture to, for example, enable direct addressing transactions as well as batch transactions across multiple microsectors. A data path disposed between programmable logic circuitry of a column of microsectors and a column of row controllers may form a micro-network-on-chip used by a network-on-chip to interface with the programmable logic circuitry.Type: ApplicationFiled: December 23, 2020Publication date: June 23, 2022Inventors: Ilya K. Ganusov, Ashish Gupta, Chee Hak Teh, Sean R. Atsatt, Scott Jeremy Weber, Parivallal Kannan, Aman Gupta, Gary Brian Wallichs
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Publication number: 20220121595Abstract: An interface bridge to enable communication between a first integrated circuit die and a second integrated circuit die is disclosed. The two integrated circuit die may be connected via chip-to-chip interconnects. The first integrated circuit die may include programmable logic fabric. The second integrated circuit die may support the first integrated circuit die. The first integrated circuit die and the secondary integrated circuit die may communicate with one another via the chip-to-chip interconnects using an interface bridge. The first and second component integrated circuits may include circuitry to implement the interface bridge, which may provide source-synchronous communication using a data receive clock from the second integrated circuit die to the first integrated circuit die.Type: ApplicationFiled: December 24, 2021Publication date: April 21, 2022Inventors: Jeffrey Erik Schulz, David W. Mendel, Dinesh D. Patil, Gary Brian Wallichs, Keith Duwel, Jakob Raymond Jones
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Publication number: 20220066977Abstract: Systems and methods are provided for supporting wide-protocol interface across a multi-die interconnect interface. Data signals of a wide-protocol interface are split into a plurality of data streams. A handshake signal is established between a first circuit and a second circuit, whereby the first circuit and second circuit are dies of a multi-die device. The first circuit transmits the plurality of data streams to the second circuit via a plurality of multi-die interconnect channels. Each data stream of the plurality of data streams are compressed based on the handshake signal in order to provide wide-protocol interface with reduced number of required pins.Type: ApplicationFiled: November 9, 2021Publication date: March 3, 2022Inventors: Gary Brian Wallichs, Keith Duwel, Cora Lynn Mau
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Patent number: 11237998Abstract: An interface bridge to enable communication between a first integrated circuit die and a second integrated circuit die is disclosed. The two integrated circuit die may be connected via chip-to-chip interconnects. The first integrated circuit die may include programmable logic fabric. The second integrated circuit die may support the first integrated circuit die. The first integrated circuit die and the secondary integrated circuit die may communicate with one another via the chip-to-chip interconnects using an interface bridge. The first and second component integrated circuits may include circuitry to implement the interface bridge, which may provide source-synchronous communication using a data receive clock from the second integrated circuit die to the first integrated circuit die.Type: GrantFiled: December 22, 2020Date of Patent: February 1, 2022Assignee: Intel CorporationInventors: Jeffrey Erik Schulz, David W. Mendel, Dinesh D. Patil, Gary Brian Wallichs, Keith Duwel, Jakob Raymond Jones
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Patent number: 11169951Abstract: Systems and methods are provided for supporting wide-protocol interface across a multi-die interconnect interface. Data signals of a wide-protocol interface are split into a plurality of data streams. A handshake signal is established between a first circuit and a second circuit, whereby the first circuit and second circuit are dies of a multi-die device. The first circuit transmits the plurality of data streams to the second circuit via a plurality of multi-die interconnect channels. Each data stream of the plurality of data streams are compressed based on the handshake signal in order to provide wide-protocol interface with reduced number of required pins.Type: GrantFiled: November 12, 2020Date of Patent: November 9, 2021Assignee: Altera CorporationInventors: Gary Brian Wallichs, Keith Duwel, Cora Lynn Mau
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Patent number: 11100029Abstract: An interface bridge to enable communication between a first integrated circuit die and a second integrated circuit die is disclosed. The two integrated circuit die may be connected via chip-to-chip interconnects. The first integrated circuit die may include programmable logic fabric. The second integrated circuit die may support the first integrated circuit die. The first integrated circuit die and the secondary integrated circuit die may communicate with one another via the chip-to-chip interconnects using an interface bridge. The first and second component integrated circuits may include circuitry to implement the interface bridge, which may provide source-synchronous communication using a data receive clock from the second integrated circuit die to the first integrated circuit die.Type: GrantFiled: August 8, 2019Date of Patent: August 24, 2021Assignee: Intel CorporationInventors: Jeffrey Erik Schulz, David W. Mendel, Dinesh D. Patil, Gary Brian Wallichs, Keith Duwel, Jakob Raymond Jones
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Publication number: 20210109883Abstract: An interface bridge to enable communication between a first integrated circuit die and a second integrated circuit die is disclosed. The two integrated circuit die may be connected via chip-to-chip interconnects. The first integrated circuit die may include programmable logic fabric. The second integrated circuit die may support the first integrated circuit die. The first integrated circuit die and the secondary integrated circuit die may communicate with one another via the chip-to-chip interconnects using an interface bridge. The first and second component integrated circuits may include circuitry to implement the interface bridge, which may provide source-synchronous communication using a data receive clock from the second integrated circuit die to the first integrated circuit die.Type: ApplicationFiled: December 22, 2020Publication date: April 15, 2021Inventors: Jeffrey Erik Schulz, David W. Mendel, Dinesh D. Patil, Gary Brian Wallichs, Keith Duwel, Jacob Raymond Jones
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Publication number: 20210064566Abstract: Systems and methods are provided for supporting wide-protocol interface across a multi-die interconnect interface. Data signals of a wide-protocol interface are split into a plurality of data streams. A handshake signal is established between a first circuit and a second circuit, whereby the first circuit and second circuit are dies of a multi-die device. The first circuit transmits the plurality of data streams to the second circuit via a plurality of multi-die interconnect channels. Each data stream of the plurality of data streams are compressed based on the handshake signal in order to provide wide-protocol interface with reduced number of required pins.Type: ApplicationFiled: November 12, 2020Publication date: March 4, 2021Inventors: Gary Brian Wallichs, Keith Duwel, Cora Lynn Mau
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Patent number: 10936531Abstract: Systems and methods are provided for supporting wide-protocol interface across a multi-die interconnect interface. Data signals of a wide-protocol interface are split into a plurality of data streams. A handshake signal is established between a first circuit and a second circuit, whereby the first circuit and second circuit are dies of a multi-die device. The first circuit transmits the plurality of data streams to the second circuit via a plurality of multi-die interconnect channels. Each data stream of the plurality of data streams are compressed based on the handshake signal in order to provide wide-protocol interface with reduced number of required pins.Type: GrantFiled: February 17, 2020Date of Patent: March 2, 2021Assignee: Altera CorporationInventors: Gary Brian Wallichs, Keith Duwel, Cora Lynn Mau
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Publication number: 20200183877Abstract: Systems and methods are provided for supporting wide-protocol interface across a multi-die interconnect interface. Data signals of a wide-protocol interface are split into a plurality of data streams. A handshake signal is established between a first circuit and a second circuit, whereby the first circuit and second circuit are dies of a multi-die device. The first circuit transmits the plurality of data streams to the second circuit via a plurality of multi-die interconnect channels. Each data stream of the plurality of data streams are compressed based on the handshake signal in order to provide wide-protocol interface with reduced number of required pins.Type: ApplicationFiled: February 17, 2020Publication date: June 11, 2020Inventors: Gary Brian Wallichs, Keith Duwel, Cora Lynn Mau
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Patent number: 10565155Abstract: Systems and methods are provided for supporting wide-protocol interface across a multi-die interconnect interface. Data signals of a wide-protocol interface are split into a plurality of data streams. A handshake signal is established between a first circuit and a second circuit, whereby the first circuit and second circuit are dies of a multi-die device. The first circuit transmits the plurality of data streams to the second circuit via a plurality of multi-die interconnect channels. Each data stream of the plurality of data streams are compressed based on the handshake signal in order to provide wide-protocol interface with reduced number of required pins.Type: GrantFiled: December 3, 2018Date of Patent: February 18, 2020Assignee: Altera CorporationInventors: Gary Brian Wallichs, Keith Duwel, Cora Lynn Mau
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Patent number: 10509757Abstract: Integrated circuits may have programmable logic circuitry and hard-coded circuitry. The hard-coded circuitry may include data circuitry, a processor, and memory. As the hard-coded circuitry has a limited capacity, a portion of the programmable logic circuitry may be configured using configuration data to serve as expanded soft-coded memory for the hard-coded processor. Instructions for controlling settings of the data circuitry may be stored on the hard-coded and soft-coded memory. An additional portion of the programmable logic circuitry may be configured using the configuration data to serve as a soft-coded processor that executes the instructions stored on the soft-coded memory. Use of the soft-coded processor and/or expanded soft-coded memory may allow for more advanced algorithms for initialization and calibration of the data circuitry than when only hard-coded memory is used and may allow for updated processor circuitry to be implemented.Type: GrantFiled: September 22, 2016Date of Patent: December 17, 2019Assignee: Altera CorporationInventors: Paul Kim, Alfredo de la Cruz, Gary Brian Wallichs, Yi Peng
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Publication number: 20190361831Abstract: An interface bridge to enable communication between a first integrated circuit die and a second integrated circuit die is disclosed. The two integrated circuit die may be connected via chip-to-chip interconnects. The first integrated circuit die may include programmable logic fabric. The second integrated circuit die may support the first integrated circuit die. The first integrated circuit die and the secondary integrated circuit die may communicate with one another via the chip-to-chip interconnects using an interface bridge. The first and second component integrated circuits may include circuitry to implement the interface bridge, which may provide source-synchronous communication using a data receive clock from the second integrated circuit die to the first integrated circuit die.Type: ApplicationFiled: August 8, 2019Publication date: November 28, 2019Inventors: Jeffrey Erik Schulz, David W. Mendel, Dinesh D. Patil, Gary Brian Wallichs, Keith Duwel, Jakob Raymond Jones
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Patent number: 10445278Abstract: An interface bridge to enable communication between a first integrated circuit die and a second integrated circuit die is disclosed. The two integrated circuit die may be connected via chip-to-chip interconnects. The first integrated circuit die may include programmable logic fabric. The second integrated circuit die may support the first integrated circuit die. The first integrated circuit die and the secondary integrated circuit die may communicate with one another via the chip-to-chip interconnects using an interface bridge. The first and second component integrated circuits may include circuitry to implement the interface bridge, which may provide source-synchronous communication using a data receive clock from the second integrated circuit die to the first integrated circuit die.Type: GrantFiled: December 28, 2016Date of Patent: October 15, 2019Assignee: Intel CorporationInventors: Jeffrey Erik Schulz, David W. Mendel, Dinesh D. Patil, Gary Brian Wallichs, Keith Duwel, Jakob Raymond Jones
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Publication number: 20190179792Abstract: Systems and methods are provided for supporting wide-protocol interface across a multi-die interconnect interface. Data signals of a wide-protocol interface are split into a plurality of data streams. A handshake signal is established between a first circuit and a second circuit, whereby the first circuit and second circuit are dies of a multi-die device. The first circuit transmits the plurality of data streams to the second circuit via a plurality of multi-die interconnect channels. Each data stream of the plurality of data streams are compressed based on the handshake signal in order to provide wide-protocol interface with reduced number of required pins.Type: ApplicationFiled: December 3, 2018Publication date: June 13, 2019Inventors: Gary Brian Wallichs, Keith Duwel, Cora Lynn Mau