Patents by Inventor Gary C. Whitlock

Gary C. Whitlock has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5577201
    Abstract: A diagnostic protocol and display system wherein the cable bus output of a computer to a printer is sensed to select coded error data out of the output stream in order to activate a visual display of coded error data for benefit of the human operator.
    Type: Grant
    Filed: September 20, 1995
    Date of Patent: November 19, 1996
    Assignee: Unisys Corporation
    Inventors: Patrick C. S. Chan, Gary C. Whitlock
  • Patent number: 5446848
    Abstract: An entry level data processing system is expandable, with low overhead, by a factor of two to a partitionable upgraded data processing system. This entry level system includes: 1) one system bus, 2) a central processing module (CPM), an input/output module (IOM), and a system control module (SCM)--all of which have one system bus port coupled to the system bus, 3) a memory module coupled via a memory bus to the system control module, and 4) a system expansion interface through which the entry level system is expanded to the upgraded system. In one particular preferred embodiment, the system expansion interface consists of a) a first connector on the SCM for externally connecting to and communicating with the memory bus, b) a second connector on the SCM for externally connecting to and communicating with the system bus, and c) an extension of the system bus through a switch in the SCM and a third connector on the SCM for externally connecting to and communicating with the extended system bus.
    Type: Grant
    Filed: June 25, 1993
    Date of Patent: August 29, 1995
    Inventors: Gary C. Whitlock, Richard D. Freeman, Keith S. Saldanha
  • Patent number: 4932028
    Abstract: A VSLI chip is implemented with registers which log permanent and intermittent errors occurring within the chip as sensed by concurrent error detection circuitry (CED). If a fatal error is detected (one which would destroy the reliability of chip operations), then the chip is immobilized into a hold mode (freeze). Interrupts are signalled to a cooperating maintenance controller which can pass the error information to an external computer for display and for locating a faulty area.
    Type: Grant
    Filed: June 21, 1988
    Date of Patent: June 5, 1990
    Assignee: Unisys Corporation
    Inventors: Haluk Katircioglu, John A. De Beule, Debaditya Mukherjee, Gary C. Whitlock