Patents by Inventor Gary Carreau

Gary Carreau has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10972063
    Abstract: Amplifier systems for measuring a wide range of current are provided herein. In certain embodiments, an amplifier system includes a controllable sensing circuit, a first amplifier including an output configured to drive a device under test (DUT) through the controllable sensing circuit, and a second amplifier including an input coupled to the controllable sensing circuit and operable to generate a measurement signal indicating an amount of measured current of the DUT. The amplifier system further includes a control circuit operable to control a configuration or mode of the controllable sensing circuit suitable for a particular type of DUT.
    Type: Grant
    Filed: October 30, 2018
    Date of Patent: April 6, 2021
    Assignee: Analog Devices Global Unlimited Company
    Inventors: Simon Nicholas Fiedler Basilico, Yoshinori Kusuda, Camille Louis Huin, Gary Carreau, Gustavo Castro, Sean Patrick Kowalik, Michael C. W. Coln, Scott Andrew Hunt
  • Publication number: 20210052232
    Abstract: There is disclosed herein a computed tomography (CT) imaging module. The CT imaging module may have a light sensor array to detect photons within a CT imaging system and may produce a plurality of signals based on the detected photons. A switching/multiplexing element may receive the plurality of signals and multiplex the plurality of signals for signal processing. The multiplexing of the plurality of signals may provide for less interconnections for the light sensors within the light sensor array, thereby reducing the risk of reliability failure of the interconnections. Further, fewer signal processing circuitry elements may be utilized for processing the plurality of signals, allowing the CT imaging module to take up less space.
    Type: Application
    Filed: August 21, 2020
    Publication date: February 25, 2021
    Applicant: Analog Devices, Inc.
    Inventors: Hung D. NGO, Gary CARREAU, Matthew A. WOODRUFF
  • Publication number: 20200394378
    Abstract: Systems and methods described herein relate to fingerprint-on-display recognition. In particular, the systems and methods described herein may recognize a fingerprint when a finger of a user is placed on a display and authenticate the user based on the recognized fingerprint. Further, the embodiments described herein may utilize multiple colors and/or secondary factors to reduce erroneous authentications of the user. The approaches may improve the accuracy of fingerprint authentication by using the multiple colors and/or secondary factors.
    Type: Application
    Filed: June 12, 2020
    Publication date: December 17, 2020
    Applicant: Analog Devices International Unlimited Company
    Inventors: Patrick Riehl, Gary Carreau, Richard J. Capistran, Kenneth M. Feen, Brian Jeffrey Wengreen
  • Publication number: 20200127624
    Abstract: Amplifier systems for measuring a wide range of current are provided herein. In certain embodiments, an amplifier system includes a controllable sensing circuit, a first amplifier including an output configured to drive a device under test (DUT) through the controllable sensing circuit, and a second amplifier including an input coupled to the controllable sensing circuit and operable to generate a measurement signal indicating an amount of measured current of the DUT. The amplifier system further includes a control circuit operable to control a configuration or mode of the controllable sensing circuit suitable for a particular type of DUT.
    Type: Application
    Filed: October 30, 2018
    Publication date: April 23, 2020
    Inventors: Simon Nicholas Fiedler Basilico, Yoshinori Kusuda, Camille Louis Huin, Gary Carreau, Gustavo Castro, Sean Patrick Kowalik, Michael C. W. Coln, Scott Andrew Hunt
  • Patent number: 8837099
    Abstract: Disclosed embodiments are directed to an electrical overstress protection circuit. The electrical overstress protection circuit may include an intermediate node receiving a reference voltage, a first pair of clamp devices, having opposite polarity, clamping an input signal line to the intermediate node, and a second pair of clamp devices, each clamping the intermediate node to one of two reference potentials. The electrical overstress protection circuit may also include a filter connected to the intermediate node to reduce noise at the intermediate node.
    Type: Grant
    Filed: December 24, 2009
    Date of Patent: September 16, 2014
    Assignee: Analog Devices, Inc.
    Inventors: Michael Coln, Gary Carreau, Yoshinori Kusuda
  • Patent number: 8754799
    Abstract: A circuit system for performing correlated double sampling may include a signal sampling stage having an amplifier with a feedback capacitor and a pair of storage capacitors coupled to an output of the amplifier, and a differential analog to digital converter (ADC) having a pair of inputs coupled respectively to storage capacitors of the signal sampling stage. The signal sampling stage may receive reset and signal values from a sensor device and may store processed versions of those signals on respective storage capacitors. The differential ADC may generate a digital value representing a signal captured by the sensor device from a differential digitization operation performed on the processed versions of the reset and signal values. In this manner, the system may correct for any signal errors introduced by components of the sampling stage.
    Type: Grant
    Filed: August 2, 2012
    Date of Patent: June 17, 2014
    Assignee: Analog Devices, Inc.
    Inventors: Michael Coln, Gary Carreau, Yoshinori Kusuda
  • Patent number: 8564464
    Abstract: Techniques to reduce correlated errors in a multi-channel sampling system. A plurality of clock signals may be generated from a master clock signal, each with edges offset from each other. The offset clock signals may be distributed to a plurality of sampling devices. Each sampling device may capture a respective input signal according to its offset clock. In this manner, the sampling units may sample their inputs signals over a distributed window of time rather than sampling in response to a common clock edge. By distributing the switching operations performed by the sampling units, noise effects are likely to be reduced.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: October 22, 2013
    Assignee: Analog Devices, Inc.
    Inventor: Gary Carreau
  • Patent number: 8514014
    Abstract: An amplifier system can include a feedback amplifier circuit having an amplifier, a feedback capacitor connected between an input terminal and an output terminal of the amplifier by at least one first switch, and a reset capacitor connected across the feedback capacitor by at least one second switch and between a pair of reference voltages by at least one third switch. During an input-signal processing phase of operation, a control circuit may close the at least one first switch and open the at least one second switch to electrically connect the feedback capacitor between the input and output terminals to engage feedback processing by the feedback amplifier circuit, and close the third switch to electrically connect the reset capacitor between the first and second voltages to charge the reset capacitor to a selectable voltage difference.
    Type: Grant
    Filed: February 9, 2011
    Date of Patent: August 20, 2013
    Assignee: Analog Devices, Inc.
    Inventors: Cathal Murphy, Michael Coln, Gary Carreau, Alain Valentin Guery, Bruce Amazeen
  • Publication number: 20130076402
    Abstract: Techniques to reduce correlated errors in a multi-channel sampling system. A plurality of clock signals may be generated from a master clock signal, each with edges offset from each other. The offset clock signals may be distributed to a plurality of sampling devices. Each sampling device may capture a respective input signal according to its offset clock. In this manner, the sampling units may sample their inputs signals over a distributed window of time rather than sampling in response to a common clock edge. By distributing the switching operations performed by the sampling units, noise effects are likely to be reduced.
    Type: Application
    Filed: September 23, 2011
    Publication date: March 28, 2013
    Applicant: ANALOG DEVICES, INC.
    Inventor: Gary CARREAU
  • Publication number: 20120200350
    Abstract: An amplifier system can include a feedback amplifier circuit having an amplifier, a feedback capacitor connected between an input terminal and an output terminal of the amplifier by at least one first switch, and a reset capacitor connected across the feedback capacitor by at least one second switch and between a pair of reference voltages by at least one third switch. During an input-signal processing phase of operation, a control circuit may close the at least one first switch and open the at least one second switch to electrically connect the feedback capacitor between the input and output terminals to engage feedback processing by the feedback amplifier circuit, and close the third switch to electrically connect the reset capacitor between the first and second voltages to charge the reset capacitor to a selectable voltage difference.
    Type: Application
    Filed: February 9, 2011
    Publication date: August 9, 2012
    Applicant: ANALOG DEVICES, INC.
    Inventors: Cathal MURPHY, Michael COLN, Gary CARREAU, Alain Valentin GUERY, Bruce AMAZEEN
  • Patent number: 8203357
    Abstract: An integrated circuit may include a plurality of circuit sub-systems that include at least one converter circuit operating in respective critical phases and non-critical phases of operation, a clock distribution circuit that has an input for an externally-supplied clock signal that is active during the non-critical phases and inactive during the critical phases, and a clock generator to generate an internal clock signal to the converter circuit that is active when the external-supplied clock signal is inactive.
    Type: Grant
    Filed: December 4, 2009
    Date of Patent: June 19, 2012
    Assignee: Analog Devices, Inc.
    Inventors: Yoshinori Kusuda, Michael Coln, Gary Carreau
  • Patent number: 8004448
    Abstract: A system for converting an analog signal to a digital codeword having N bit positions that includes a dual DAC structure having a small DAC and a large DAC. At least one comparator is coupled to the small DAC and large DAC. The small DAC performs bit trials to calculate bit positions 1 to M, and the large DAC with performs bit trial calculates bit positions M+1 to N after having been set with bit decisions from the bit trials of the small DAC.
    Type: Grant
    Filed: November 16, 2009
    Date of Patent: August 23, 2011
    Assignee: Analog Devices, Inc.
    Inventor: Gary Carreau
  • Patent number: 7982643
    Abstract: An analog-to-digital conversion system includes an analog-to-digital converter (ADC), a plurality of receivers, each for capturing input analog signals, a multiplexer having inputs coupled to each of the receivers and an output coupled to the ADC, the multiplexer establishing a signal path between a selected one of the inputs and the output in response to an index signal, and a mux controller to supply a random sequence of index signals to the multiplexer.
    Type: Grant
    Filed: November 20, 2009
    Date of Patent: July 19, 2011
    Assignee: Analog Devices, Inc.
    Inventor: Gary Carreau
  • Publication number: 20110115658
    Abstract: A system for converting an analog signal to a digital codeword having N bit positions that includes a dual DAC structure having a small DAC and a large DAC. At least one comparator is coupled to the small DAC and large DAC. The small DAC performs bit trials to calculate bit positions 1 to M, and the large DAC with performs bit trial calculates bit positions M+1 to N after having been set with bit decisions from the bit trials of the small DAC.
    Type: Application
    Filed: November 16, 2009
    Publication date: May 19, 2011
    Applicant: ANALOG DEVICES, INC.
    Inventor: Gary Carreau
  • Publication number: 20110043251
    Abstract: An integrated circuit may include a plurality of circuit sub-systems that include at least one converter circuit operating in respective critical phases and non-critical phases of operation, a clock distribution circuit that has an input for an externally-supplied clock signal that is active during the non-critical phases and inactive during the critical phases, and a clock generator to generate an internal clock signal to the converter circuit that is active when the external-supplied clock signal is inactive.
    Type: Application
    Filed: December 4, 2009
    Publication date: February 24, 2011
    Inventors: Yoshinori Kusuda, Michael Coln, Gary Carreau
  • Publication number: 20110043397
    Abstract: An analog-to-digital conversion system includes an analog-to-digital converter (ADC), a plurality of receivers, each for capturing input analog signals, a multiplexer having inputs coupled to each of the receivers and an output coupled to the ADC, the multiplexer establishing a signal path between a selected one of the inputs and the output in response to an index signal, and a mux controller to supply a random sequence of index signals to the multiplexer.
    Type: Application
    Filed: November 20, 2009
    Publication date: February 24, 2011
    Applicant: ANALOG DEVICES, INC.
    Inventor: Gary CARREAU
  • Publication number: 20110038083
    Abstract: Disclosed embodiments are directed to an electrical overstress protection circuit. The electrical overstress protection circuit may include an intermediate node receiving a reference voltage, a first pair of clamp devices, having opposite polarity, clamping an input signal line to the intermediate node, and a second pair of clamp devices, each clamping the intermediate node to one of two reference potentials. The electrical overstress protection circuit may also include a filter connected to the intermediate node to reduce noise at the intermediate node.
    Type: Application
    Filed: December 24, 2009
    Publication date: February 17, 2011
    Applicant: ANALOG DEVICES, INC.
    Inventors: Michael COLN, Gary CARREAU, Yoshinori KUSUDA
  • Patent number: 7843373
    Abstract: A system for randomizing aperture delay in a time interleaved ADC system that includes a plurality of selection switch stages corresponding to each of the ADCs in the system and a second selection switch stage coupled to a voltage source. A plurality of conductors extend between the second selection switch stage and each of the selection switch stages, in excess of the number of ADCs in the system. For each of N ADCs in the system, the selection switch stages and the second selection switch stage support at least N+1 selectable conductive paths extending from each of the sampling capacitors of the ADCs to the voltage source. Random selection of the N+1 paths can randomize aperture delay.
    Type: Grant
    Filed: February 27, 2009
    Date of Patent: November 30, 2010
    Assignee: Analog Devices, Inc.
    Inventor: Gary Carreau
  • Patent number: 7834793
    Abstract: An SAR analog-to-digital converter performs bit decisions in each of a plurality of clock cycles. A sense circuit monitors signals input to a latch within a comparator of the ADC and, when the signals are sufficient to establish a bit decision, the sense circuit terminates a currently active clock cycle causes a bit decision to occur in advance of a normal expiration of the clock cycle. If the signals are insufficient to establish a bit decision prior to a default expiration time of the clock cycle, the clock cycle concludes at the default expiration time.
    Type: Grant
    Filed: November 26, 2008
    Date of Patent: November 16, 2010
    Assignee: Analog Devices, Inc.
    Inventors: Gary Carreau, Bruce Amazeen
  • Publication number: 20100220000
    Abstract: A system for randomizing aperture delay in a time interleaved ADC system that includes a plurality of selection switch stages corresponding to each of the ADCs in the system and a second selection switch stage coupled to a voltage source. A plurality of conductors extend between the second selection switch stage and each of the selection switch stages, in excess of the number of ADCs in the system. For each of N ADCs in the system, the selection switch stages and the second selection switch stage support at least N+1 selectable conductive paths extending from each of the sampling capacitors of the ADCs to the voltage source. Random selection of the N+1 paths can randomize aperture delay.
    Type: Application
    Filed: February 27, 2009
    Publication date: September 2, 2010
    Applicant: ANALOG DEVICES, INC.
    Inventor: Gary CARREAU