Patents by Inventor Gary Chan

Gary Chan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250261436
    Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The method can include forming a fin structure over a substrate. The fin structure can include a channel layer and a sacrificial layer. The method can further include forming a first recess structure in a first portion of the fin structure, forming a second recess structure in the sacrificial layer of a second portion of the fin structure, forming a dielectric layer in the first and second recess structures, and performing an oxygen-free cyclic etching process to etch the dielectric layer to expose the channel layer of the second portion of the fin structure. The oxygen-free cyclic etching process can include two etching processes to selectively etch the dielectric layer over the channel layer.
    Type: Application
    Filed: April 2, 2025
    Publication date: August 14, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Han-Yu LIN, Jhih-Rong HUANG, Yen-Tien TUNG, Tzer-Min SHEN, Fu-Ting YEN, Gary CHAN, Keng-Chu LIN, Li-Te LIN, Pinyen LIN
  • Patent number: 12288722
    Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The method can include forming a fin structure over a substrate. The fin structure can include a channel layer and a sacrificial layer. The method can further include forming a first recess structure in a first portion of the fin structure, forming a second recess structure in the sacrificial layer of a second portion of the fin structure, forming a dielectric layer in the first and second recess structures, and performing an oxygen-free cyclic etching process to etch the dielectric layer to expose the channel layer of the second portion of the fin structure. The oxygen-free cyclic etching process can include two etching processes to selectively etch the dielectric layer over the channel layer.
    Type: Grant
    Filed: January 2, 2023
    Date of Patent: April 29, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Han-Yu Lin, Jhih-Rong Huang, Yen-Tien Tung, Tzer-Min Shen, Fu-Ting Yen, Gary Chan, Keng-Chu Lin, Li-Te Lin, Pinyen Lin
  • Publication number: 20230141093
    Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The method can include forming a fin structure over a substrate. The fin structure can include a channel layer and a sacrificial layer. The method can further include forming a first recess structure in a first portion of the fin structure, forming a second recess structure in the sacrificial layer of a second portion of the fin structure, forming a dielectric layer in the first and second recess structures, and performing an oxygen-free cyclic etching process to etch the dielectric layer to expose the channel layer of the second portion of the fin structure. The oxygen-free cyclic etching process can include two etching processes to selectively etch the dielectric layer over the channel layer.
    Type: Application
    Filed: January 2, 2023
    Publication date: May 11, 2023
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Han-Yu LIN, Jhih-Rong HUANG, Yen-Tien TUNG, Tzer-Min SHEN, Fu-Ting YEN, Gary CHAN, Keng-Chu LIN, Li-Te LIN, Pinyen LIN
  • Patent number: 11545397
    Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The method can include forming a fin structure over a substrate. The fin structure can include a channel layer and a sacrificial layer. The method can further include forming a first recess structure in a first portion of the fin structure, forming a second recess structure in the sacrificial layer of a second portion of the fin structure, forming a dielectric layer in the first and second recess structures, and performing an oxygen-free cyclic etching process to etch the dielectric layer to expose the channel layer of the second portion of the fin structure. The oxygen-free cyclic etching process can include two etching processes to selectively etch the dielectric layer over the channel layer.
    Type: Grant
    Filed: January 7, 2021
    Date of Patent: January 3, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Han-Yu Lin, Jhih-Rong Huang, Yen-Tien Tung, Tzer-Min Shen, Fu-Ting Yen, Gary Chan, Keng-Chu Lin, Li-Te Lin, Pinyen Lin
  • Publication number: 20220020644
    Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The method can include forming a fin structure over a substrate. The fin structure can include a first channel layer and a sacrificial layer. The method can further include forming a first recess structure in a first portion of the fin structure, forming a second recess structure in the sacrificial layer of a second portion of the fin structure, forming a dielectric layer in the first and second recess structures, and performing an oxygen-free cyclic etching process to etch the dielectric layer to expose the channel layer of the second portion of the fin structure.
    Type: Application
    Filed: January 7, 2021
    Publication date: January 20, 2022
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Han-Yu LIN, Jhih-Rong Huang, Yen-Tien Tung, Tzer-Min Shen, Fu-Ting Yen, Gary Chan, Keng-Chu Lin, Li-Te Lin, Pinyen Lin
  • Patent number: 11096311
    Abstract: Various implementations disclosed herein include a thermal management system suitable electronic devices. In some implementations, a thermal management system includes an air guide and a cage wall, which together provide: an air intake having a first airflow area to produce a first air pressure; an airflow constriction, following the air intake, having a second airflow area smaller than the first airflow area to produce a second air pressure, and defining a first region; and an outlet following the airflow constriction having a third airflow area greater than the second airflow area to produce a third air pressure. The device cage has at least one aperture in the first region. The second air pressure is less than the first air pressure and the third air pressure and is sufficiently low to draw heated air from within the device cage through the at least one aperture to be expelled through the outlet.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: August 17, 2021
    Assignee: Cisco Technology, Inc.
    Inventors: Perry L. Hayden, Gary Chan, Bob Dillman
  • Publication number: 20190200480
    Abstract: Various implementations disclosed herein include a thermal management system suitable electronic devices. In some implementations, a thermal management system includes an air guide and a cage wall, which together provide: an air intake having a first airflow area to produce a first air pressure; an airflow constriction, following the air intake, having a second airflow area smaller than the first airflow area to produce a second air pressure, and defining a first region; and an outlet following the airflow constriction having a third airflow area greater than the second airflow area to produce a third air pressure. The device cage has at least one aperture in the first region. The second air pressure is less than the first air pressure and the third air pressure and is sufficiently low to draw heated air from within the device cage through the at least one aperture to be expelled through the outlet.
    Type: Application
    Filed: December 19, 2018
    Publication date: June 27, 2019
    Inventors: Perry L. Hayden, Gary Chan, Bob Dillman
  • Patent number: 10194557
    Abstract: Various implementations disclosed herein include a thermal management system suitable electronic devices. In some implementations, a thermal management system includes an air guide and a cage wall, which together provide: an air intake having a first airflow area to produce a first air pressure; an airflow constriction, following the air intake, having a second airflow area smaller than the first airflow area to produce a second air pressure, and defining a first region; and an outlet following the airflow constriction having a third airflow area greater than the second airflow area to produce a third air pressure. The device cage has at least one aperture in the first region. The second air pressure is less than the first air pressure and the third air pressure and is sufficiently low to draw heated air from within the device cage through the at least one aperture to be expelled through the outlet.
    Type: Grant
    Filed: February 12, 2015
    Date of Patent: January 29, 2019
    Assignee: CISCO TECHNOLOGY, INC.
    Inventors: Perry L. Hayden, Sr., Gary Chan, Bob Dillman
  • Publication number: 20160242317
    Abstract: Various implementations disclosed herein include a thermal management system suitable electronic devices. In some implementations, a thermal management system includes an air guide and a cage wall, which together provide: an air intake having a first airflow area to produce a first air pressure; an airflow constriction, following the air intake, having a second airflow area smaller than the first airflow area to produce a second air pressure, and defining a first region; and an outlet following the airflow constriction having a third airflow area greater than the second airflow area to produce a third air pressure. The device cage has at least one aperture in the first region. The second air pressure is less than the first air pressure and the third air pressure and is sufficiently low to draw heated air from within the device cage through the at least one aperture to be expelled through the outlet.
    Type: Application
    Filed: February 12, 2015
    Publication date: August 18, 2016
    Inventors: Perry L. Hayden, SR., Gary Chan, Bob Dillman
  • Publication number: 20140279368
    Abstract: A method and system for a GCF repo swap transaction includes generating an index using a limited set of GCF contracts, and using the index value as a value in a GCF repo swap. The index value may be used as a variable or floating value in the swap, or may be used at the fixed value in the swap.
    Type: Application
    Filed: March 17, 2014
    Publication date: September 18, 2014
    Applicant: The Depository Trust and Clearing Corporation (DTCC)
    Inventor: Gary Chan
  • Patent number: 8606428
    Abstract: In order to adequately but not excessively or unnecessarily cool heat generating electrical components and decrease the noise produced by fans used to cool the heat generating electrical components in an electrical hardware system, an environmental controller controls the speeds of the fans using at least two temperature sensors. In one example, a first temperature sensor measures a hotspot component temperature and generates a hotspot component temperature value, and a second temperature sensor measures an air inlet temperature and generates an air inlet temperature value. The environmental controller controls the speeds of the fans based on the difference between the measured hotspot component temperature value and a target hotspot component temperature value calculated based on the measured air inlet temperature value and a predefined function.
    Type: Grant
    Filed: February 25, 2011
    Date of Patent: December 10, 2013
    Assignee: Cisco Technology, Inc.
    Inventor: Gary Chan
  • Publication number: 20120218707
    Abstract: In order to adequately but not excessively or unnecessarily cool heat generating electrical components and decrease the noise produced by fans used to cool the heat generating electrical components in an electrical hardware system, an environmental controller controls the speeds of the fans using at least two temperature sensors. In one example, a first temperature sensor measures a hotspot component temperature and generates a hotspot component temperature value, and a second temperature sensor measures an air inlet temperature and generates an air inlet temperature value. The environmental controller controls the speeds of the fans based on the difference between the measured hotspot component temperature value and a target hotspot component temperature value calculated based on the measured air inlet temperature value and a predefined function.
    Type: Application
    Filed: February 25, 2011
    Publication date: August 30, 2012
    Inventor: GARY CHAN
  • Patent number: 8119378
    Abstract: The invention relates to the production of alcohols by microbial fermentation, particularly to production of alcohols by microbial fermentation of substrates comprising CO. It more particularly relates to processes for the production of alcohols from their corresponding acids in the presence of a substrate comprising CO. In particular embodiments, a fermentation reaction producing acid(s) and optionally alcohol(s) is perturbed such that at least a portion one or more of acid(s) is converted to alcohol.
    Type: Grant
    Filed: February 18, 2009
    Date of Patent: February 21, 2012
    Assignee: LanzaTech New Zealand Limited
    Inventors: Sean Dennis Simpson, Christophe Collet, Phuong Loan Tran, Bakir Al-Sinawi, Richard Llewellyn Sydney Forster, Matthew James Rowe, Gary Chan, Kelly Marie Mahar, Jennifer Mon Yee Fung
  • Publication number: 20110059499
    Abstract: The invention relates to the production of alcohols by microbial fermentation, particularly to production of alcohols by microbial fermentation of substrates comprising CO. It more particularly relates to processes for the production of alcohols from their corresponding acids in the presence of a substrate comprising CO. In particular embodiments, a fermentation reaction producing acid(s) and optionally alcohol(s) is perturbed such that at least a portion one or more of acid(s) is converted to alcohol.
    Type: Application
    Filed: February 18, 2009
    Publication date: March 10, 2011
    Applicant: Lanza Tech New Zealand Limited
    Inventors: Sean Dennis Simpson, Christophe Collet, Phuong Loan Tran, Bakir Al-Sinawi, Richard Llewellyn Sydney Forster, Matthew James Rowe, Gary Chan, Kelly Marie Mahar, Jennifer Mon Yee Fung
  • Patent number: 7612605
    Abstract: A bootstrap voltage generating circuit includes a bias circuit having a first end coupled to a first power source node having an operation voltage, and a second end coupled to a low voltage reference potential, wherein a voltage at the first end is related to the operation voltage in a non-linear way; a charging capacitor having a first end coupled to the load circuit; a charging path between a second end of the charging capacitor and the first end of the bias circuit, wherein the charging path is responsive to a clock signal; a discharging path between the second end of the charging capacitor and the low voltage reference potential, wherein the discharging path is responsive to the clock signal; and a switch circuit connected to the first end of the charging capacitor for setting a voltage thereon, wherein the switch circuit is responsive to the clock signal.
    Type: Grant
    Filed: February 12, 2007
    Date of Patent: November 3, 2009
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shao-Yu Chou, Yen-Huei Chen, Jui-Jen Wu, Gary Chan
  • Publication number: 20080191798
    Abstract: A bootstrap voltage generating circuit includes a bias circuit having a first end coupled to a first power source node having an operation voltage, and a second end coupled to a low voltage reference potential, wherein a voltage at the first end is related to the operation voltage in a non-linear way; a charging capacitor having a first end coupled to the load circuit; a charging path between a second end of the charging capacitor and the first end of the bias circuit, wherein the charging path is responsive to a clock signal; a discharging path between the second end of the charging capacitor and the low voltage reference potential, wherein the discharging path is responsive to the clock signal; and a switch circuit connected to the first end of the charging capacitor for setting a voltage thereon, wherein the switch circuit is responsive to the clock signal.
    Type: Application
    Filed: February 12, 2007
    Publication date: August 14, 2008
    Inventors: Shao-Yu Chou, Yen-Huei Chen, Jui-Jen Wu, Gary Chan
  • Publication number: 20070206947
    Abstract: A method for negotiating speed between a Fibre Channel (FC) local client and a remote FC client across a DWDM network is provided. A transmission speed of the local FC client at a local ingress transport interface is detected. The data from the local FC client is forwarded along with the detected transmission speed to a remote egress transport interface. The remote egress interface forwards the data at the detected transmission speed to the remote FC client. The present invention eliminates complex speed negotiation state machines that would otherwise be required to make the DWDM transport behave like a virtual wire with respect to the FC ports and to allow the FC clients to negotiate the desired speed directly between themselves.
    Type: Application
    Filed: March 6, 2006
    Publication date: September 6, 2007
    Applicant: CISCO TECHNOLOGY, INC.
    Inventors: Sriram Natarajan, Jayakrishna Menon, Gary Chan
  • Publication number: 20060045165
    Abstract: A thermal interface material characterization system comprises two thermal heads. A thermal interface material is disposed between the thermal heads. A plurality of thermal sensors is disposed within one of the thermal heads. Another plurality of thermal sensors is disposed within the other thermal head. The thermal sensors generate temperature data along an axis in a direction of heat flow through the thermal heads. A thermal characteristic of the thermal interface material can be determined from the temperature data generated from the thermal sensors.
    Type: Application
    Filed: August 30, 2004
    Publication date: March 2, 2006
    Inventors: Gary Chan, Don Nguyen
  • Publication number: 20050172302
    Abstract: Disclosed is a method, system, program, and data structure for controlling access to a sensitive function in a class. A friend object is generated indicating at least one external function from at least one external class external to the class including the sensitive function. A call from a calling function in a class external to the class including the sensitive function is processed and the calling function is permitted access to the sensitive function in response to determining that the friend object indicates that the calling function can access the sensitive function.
    Type: Application
    Filed: March 23, 2005
    Publication date: August 4, 2005
    Inventors: Gary Chan, Lynda Hansen, Chi-Pei Hsing