Patents by Inventor Gary Chard
Gary Chard has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230412211Abstract: At least some aspects of the present disclosure provide for a method. In some examples, the method includes receiving 2-line data in an embedded Universal Serial Bus (eUSB) format. The method further includes encoding the 2-line data into a single signal. The single signal comprises a first symbol corresponding to a first state change of the 2-line data and a second symbol corresponding to a second state change of the 2-line data.Type: ApplicationFiled: September 6, 2023Publication date: December 21, 2023Inventors: Suzanne Mary VINING, Gary CHARD, Win Naing MAUNG, Mark Alan McADAMS
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Patent number: 11791863Abstract: At least some aspects of the present disclosure provide for a method. In some examples, the method includes receiving 2-line data in an embedded Universal Serial Bus (eUSB) format. The method further includes encoding the 2-line data into a single signal. The single signal comprises a first symbol corresponding to a first state change of the 2-line data and a second symbol corresponding to a second state change of the 2-line data.Type: GrantFiled: August 27, 2021Date of Patent: October 17, 2023Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Suzanne Mary Vining, Gary Chard, Win Naing Maung, Mark Alan McAdams
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Patent number: 11372798Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to transition devices between operational modes. An example apparatus comprising: an activity detector configured to be coupled to a communication bus; a communication bus controller coupled to the activity detector; a hardware wakeup controller coupled to the activity detector; a switching circuit coupled to the hardware wakeup controller; a first oscillator coupled to the switching circuit; and a second oscillator the second oscillator coupled to the switching circuit and the hardware wakeup controller.Type: GrantFiled: September 18, 2020Date of Patent: June 28, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Chung San Roger Chan, T-Pinn Koh, Gary Chard, Bennett Lau, Adam Rappoport
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Publication number: 20210391893Abstract: At least some aspects of the present disclosure provide for a method. In some examples, the method includes receiving 2-line data in an embedded Universal Serial Bus (eUSB) format. The method further includes encoding the 2-line data into a single signal. The single signal comprises a first symbol corresponding to a first state change of the 2-line data and a second symbol corresponding to a second state change of the 2-line data.Type: ApplicationFiled: August 27, 2021Publication date: December 16, 2021Inventors: Suzanne Mary VINING, Gary CHARD, Win Naing MAUNG, Mark Alan McADAMS
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Patent number: 11133841Abstract: At least some aspects of the present disclosure provide for a method. In some examples, the method includes receiving 2-line data in an embedded Universal Serial Bus (eUSB) format. The method further includes encoding the 2-line data into a single signal. The single signal comprises a first symbol corresponding to a first state change of the 2-line data and a second symbol corresponding to a second state change of the 2-line data.Type: GrantFiled: January 31, 2020Date of Patent: September 28, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Suzanne Mary Vining, Gary Chard, Win Naing Maung, Mark Alan McAdams
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Publication number: 20210004346Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to transition devices between operational modes. An example apparatus comprising: an activity detector configured to be coupled to a communication bus; a communication bus controller coupled to the activity detector; a hardware wakeup controller coupled to the activity detector; a switching circuit coupled to the hardware wakeup controller; a first oscillator coupled to the switching circuit; and a second oscillator the second oscillator coupled to the switching circuit and the hardware wakeup controller.Type: ApplicationFiled: September 18, 2020Publication date: January 7, 2021Inventors: Chung San Roger Chan, T-Pinn Koh, Gary Chard, Bennett Lau, Adam Rappoport
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Patent number: 10795850Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to transition devices between operational modes. An example apparatus comprising: an activity detector configured to be coupled to a communication bus; a communication bus controller coupled to the activity detector; a hardware wakeup controller coupled to the activity detector; a switching circuit coupled to the hardware wakeup controller; a first oscillator coupled to the switching circuit; and a second oscillator the second oscillator coupled to the switching circuit and the hardware wakeup controller.Type: GrantFiled: February 26, 2019Date of Patent: October 6, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Chung San Roger Chan, T-Pinn Koh, Gary Chard, Bennett Lau, Adam Rappoport
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Publication number: 20200313723Abstract: At least some aspects of the present disclosure provide for a method. In some examples, the method includes receiving 2-line data in an embedded Universal Serial Bus (eUSB) format. The method further includes encoding the 2-line data into a single signal. The single signal comprises a first symbol corresponding to a first state change of the 2-line data and a second symbol corresponding to a second state change of the 2-line data.Type: ApplicationFiled: January 31, 2020Publication date: October 1, 2020Inventors: Suzanne Mary VINING, Gary CHARD, Win Naing MAUNG, Mark Alan McADAMS
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Publication number: 20200272592Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to transition devices between operational modes. An example apparatus comprising: an activity detector configured to be coupled to a communication bus; a communication bus controller coupled to the activity detector; a hardware wakeup controller coupled to the activity detector; a switching circuit coupled to the hardware wakeup controller; a first oscillator coupled to the switching circuit; and a second oscillator the second oscillator coupled to the switching circuit and the hardware wakeup controller.Type: ApplicationFiled: February 26, 2019Publication date: August 27, 2020Inventors: Chung San Roger Chan, T-Pinn Koh, Gary Chard, Bennett Lau, Adam Rappoport
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Publication number: 20070268165Abstract: A system for presenting serial drive signals for effecting communication of parallel data signals includes: a controller; a serializer coupled with the controller; and a tri-state logic device coupled with the serializer. The controller provides parallel logic state signals to the serializer. The serializer treats the parallel data signals to present a serial data signal representing the parallel data signals at a first output locus, and treats the parallel logic state signals to present a serial logic state signal representing the parallel logic state signals at a second output locus. The tri-state logic device receives the serial data signal and the serial logic state signal for logical evaluation. The tri-state logic device presents the serial drive signals at a third output locus. Each respective drive signal has a respective drive state. Each respective drive state is determined by the logical evaluation.Type: ApplicationFiled: May 17, 2006Publication date: November 22, 2007Inventors: Gary Chard, T-Pinn Koh
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Publication number: 20050251779Abstract: A computer program (100, 200) encoded in a computer-programmable medium, and for causing a computer to perform circuit design. The code causes the computer to perform a set of steps. The steps comprise describing a first set of circuitry and describing a second set of circuitry. The steps also comprise describing a digital signal for passing from the first set of circuitry to the second set of circuitry and detecting (230) transitions of the digital signal with respect to a timing constraint (240) of at least a portion of the second set of circuitry. Lastly, the steps comprise, responsive to detecting metastability with respect to timing of a transition of the digital signal relative to the timing constraint of at least a portion of the second set of circuitry, forcing (160) the digital signal to a random value and passing the random value to the second set of circuitry.Type: ApplicationFiled: May 4, 2004Publication date: November 10, 2005Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Gary Chard, Osman Koyuncu, T-Pinn Koh, Steve Dondershine
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Publication number: 20050122793Abstract: An electronic device (10). The device comprises a memory structure (12) structure comprising an integer M of word storage locations. The device further comprises a shift register (SRRD; SRWT) for storing a sequence of bits. The sequence in the shift register comprises a number of bits equal to a ratio of 1/R1 times the integer M. The device further comprises circuitry (16) for providing a clock cycle to the shift register for selected data operations with respect to any of the word storage locations. The selected data operations are a data read or a data write. In response to each clock cycle, received from the circuitry for providing the clock cycle, the shift register shifts the sequence. Further, one bit in the sequence corresponds to an indication of one of the memory word storage locations from which a word will be read or into which a word will be written.Type: ApplicationFiled: December 3, 2003Publication date: June 9, 2005Inventors: Gary Chard, T-Pinn Koh, Osman Koyuncu
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Publication number: 20050122794Abstract: An electronic device (10). The device comprises a memory structure (12) comprising an integer M of word storage locations. The device further comprises a write shift register (SRWT) for storing a sequence of bits. The sequence in the write shift register comprises a number of bits equal to a ratio of 1/R1 times the integer M. The device further comprises circuitry (16) for providing a write clock cycle to the write shift register for selected write operations with respect to any of the word storage locations. In response to each write clock cycle, received from the circuitry for providing the write clock cycle, the write shift register shifts the sequence in the write shift register. Further, one bit in the sequence in the write shift register corresponds to an indication of one of the memory word storage locations into which a word will be written. The device further comprises a read shift register (SRRD) for storing a sequence of bits.Type: ApplicationFiled: December 3, 2003Publication date: June 9, 2005Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Gary Chard, Osman Koyuncu, T-Pinn Koh, Christopher Opoczynski