Patents by Inventor Gary Chunshien Wu
Gary Chunshien Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240136909Abstract: Circuitry and methods for an improved gate driver circuit for power converters. The improved gate driver circuit substantially reduces propagation delay and transition losses in the floating-gate side of the gate driver circuit. One embodiment includes an inverter having an input configured to receive a state transition signal and an output configured to be coupled to a control input of a switching device. The inverter includes a first NFET having a control gate configured to be coupled to the state transition signal, a second NFET having a control gate coupled to the output of a reference circuit, and a PFET having a control gate configured to be coupled to the state transition signal, wherein the output of the inverter is a node between the conduction channels of the first NFET and the second NFET and the conduction channels of the first NFET, second NFET, and PFET are coupled in series.Type: ApplicationFiled: October 18, 2022Publication date: April 25, 2024Inventor: Gary Chunshien Wu
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Patent number: 11881782Abstract: Multi-level DC-to-DC converter circuits and methods that permit a full range of output voltages, including near and at zone boundaries. Embodiments alternate among adjacent or near-by zones, operating in a first zone for a selected time and then in a second zone for a selected time. Embodiments may include a parallel capacitor voltage balancing circuit that connects a capacitor to a source voltage to charge that capacitor, or couples two or more capacitors together to transfer charge, all under the control of real-time capacitor voltage measurements. Embodiments may include a lossless voltage balancing solution where out-of-order state transitions are allowed, thus increasing or decreasing the voltage across specific capacitors to prevent voltage overstress on the converter main switches. Restrictions may be placed on the overall sequence of state transitions to reduce or avoid transition state toggling, allowing each capacitor an opportunity to have its voltage steered as necessary for balancing.Type: GrantFiled: July 15, 2021Date of Patent: January 23, 2024Assignee: pSemi CorporationInventors: Gary Chunshien Wu, David M. Giuliano, Gregory Szczeszynski
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Publication number: 20230387796Abstract: Power converter circuits and methods that include self-timed bootstrap capacitor power sources. Added to a power converter having a diode stack for charging bootstrap capacitors are three types of supplemental circuit blocks: a trigger block, a trigger-bypass block, and a bypass block. In operation, adjacent supplemental circuit blocks work in pairs. The upper block of the pair functions, when triggered, to charge an associated bootstrap capacitor by connecting the top plate of its associated bootstrap capacitor to the top plate of the bootstrap capacitor associated with the lower block of the pair, essentially bypassing the diode associated with the upper block. In addition, the lower block of the pair functions to initiate (trigger) the bypass function of the upper block. The bypass function of the upper block automatically terminates when the connected bootstrap capacitors are disconnected and their respective voltages “fly” apart, or is controllably terminated.Type: ApplicationFiled: May 24, 2022Publication date: November 30, 2023Inventors: Gary Chunshien Wu, Gregory Szczeszynski
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Publication number: 20230344352Abstract: Circuits and methods for providing a “bootstrap” power supply for level-shifter/driver (LS/D) circuits in a FET-based power converter. In a first embodiment, linear regulators and a bootstrap capacitor provide a bootstrap power supply for level-shifter/driver circuits in each tier of a multi-level FET-based power converter. In a second embodiment, floating charge circuits and bootstrap capacitors provide an improved bootstrap power supply for level-shifter and driver circuits in each tier of a multi-level FET-based power converter. More particularly, a floating charge circuit configured to be coupled to an associated bootstrap capacitor includes a first sub-circuit configured to pre-charge the associated bootstrap capacitor when coupled and a second sub-circuit configured to transfer charge between the bootstrap capacitor and a bootstrap capacitor coupled to an adjacent floating charge circuit.Type: ApplicationFiled: April 26, 2023Publication date: October 26, 2023Inventor: Gary Chunshien Wu
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Publication number: 20230223847Abstract: A current mirror circuit that allows for fast ramp-up of current for an output, thereby enabling a fast-switched current source with limited current during startup. One embodiment includes first and second transistors coupled in a current mirror configuration; a third transistor including a gate configured to be coupled to an input node, and having a conduction channel coupled between a first voltage source and the gates of the first and second transistors; a fourth transistor coupled to a second voltage source and a gate configured to be coupled to the input node; a fifth transistor including a conduction channel coupled between the conduction channels of the second and fourth transistors, and a gate coupled to a bias circuit; and a capacitor coupled between the gate of the fifth transistor and the drains of the fifth and fourth transistors.Type: ApplicationFiled: November 4, 2022Publication date: July 13, 2023Inventor: Gary Chunshien Wu
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Patent number: 11658654Abstract: Systems, methods, and apparatus for use in biasing and driving high voltage semiconductor devices using only low voltage transistors are described. The apparatus and method are adapted to control multiple high voltage semiconductor devices to enable high voltage power control, such as power amplifiers, power management and conversion (e.g. DC/DC) and other applications wherein a first voltage is large compared to the maximum voltage handling of the low voltage control transistors. According to an aspect, timing control of edges of a control signal to the high voltage semiconductor devices is provided by a basic edge delay circuit that includes a transistor, a current source and a capacitor. An inverter can be selectively coupled, via a switch, to an input and/or an output of the basic edge delay circuit to allow for timing control of a rising edge or a falling edge of the control signal.Type: GrantFiled: April 8, 2021Date of Patent: May 23, 2023Assignee: pSemi CorporationInventor: Gary Chunshien Wu
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Patent number: 11646665Abstract: Circuits and methods for providing a “bootstrap” power supply for level-shifter/driver (LS/D) circuits in a FET-based power converter. In a first embodiment, linear regulators and a bootstrap capacitor provide a bootstrap power supply for level-shifter/driver circuits in each tier of a multi-level FET-based power converter. In a second embodiment, floating charge circuits and bootstrap capacitors provide an improved bootstrap power supply for level-shifter and driver circuits in each tier of a multi-level FET-based power converter. More particularly, a floating charge circuit configured to be coupled to an associated bootstrap capacitor includes a first sub-circuit configured to pre-charge the associated bootstrap capacitor when coupled and a second sub-circuit configured to transfer charge between the bootstrap capacitor and a bootstrap capacitor coupled to an adjacent floating charge circuit.Type: GrantFiled: December 22, 2021Date of Patent: May 9, 2023Assignee: pSemi CorporationInventor: Gary Chunshien Wu
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Publication number: 20220416664Abstract: Circuits and methods for providing a “bootstrap” power supply for level-shifter/driver (LS/D) circuits in a FET-based power converter. In a first embodiment, linear regulators and a bootstrap capacitor provide a bootstrap power supply for level-shifter/driver circuits in each tier of a multi-level FET-based power converter. In a second embodiment, floating charge circuits and bootstrap capacitors provide an improved bootstrap power supply for level-shifter and driver circuits in each tier of a multi-level FET-based power converter. More particularly, a floating charge circuit configured to be coupled to an associated bootstrap capacitor includes a first sub-circuit configured to pre-charge the associated bootstrap capacitor when coupled and a second sub-circuit configured to transfer charge between the bootstrap capacitor and a bootstrap capacitor coupled to an adjacent floating charge circuit.Type: ApplicationFiled: December 22, 2021Publication date: December 29, 2022Inventor: Gary Chunshien Wu
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Patent number: 11277130Abstract: Systems, methods, and apparatus for biasing a high speed and high voltage driver using only low voltage transistors are described. The apparatus and method are adapted to control biasing voltages to the low voltage transistors such as not to exceed operating voltages of the low voltage transistors while allowing for DC to high speed operation of the driver at high voltage. A stackable and modular architecture of the driver and biasing stages is provided which can grow with a higher voltage requirement of the driver. Capacitive voltage division is used for high speed bias voltage regulation during transient phases of the driver, and resistive voltage division is used to provide bias voltage at steady state. A simpler open-drain configuration is also presented which can be used in pull-up or pull-down modes.Type: GrantFiled: September 15, 2020Date of Patent: March 15, 2022Assignee: pSemi CorporationInventor: Gary Chunshien Wu
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Publication number: 20220006382Abstract: Multi-level DC-to-DC converter circuits and methods that permit a full range of output voltages, including near and at zone boundaries. Embodiments alternate among adjacent or near-by zones, operating in a first zone for a selected time and then in a second zone for a selected time. Embodiments may include a parallel capacitor voltage balancing circuit that connects a capacitor to a source voltage to charge that capacitor, or couples two or more capacitors together to transfer charge, all under the control of real-time capacitor voltage measurements. Embodiments may include a lossless voltage balancing solution where out-of-order state transitions are allowed, thus increasing or decreasing the voltage across specific capacitors to prevent voltage overstress on the converter main switches. Restrictions may be placed on the overall sequence of state transitions to reduce or avoid transition state toggling, allowing each capacitor an opportunity to have its voltage steered as necessary for balancing.Type: ApplicationFiled: July 15, 2021Publication date: January 6, 2022Inventors: Gary Chunshien Wu, David M. Giuliano, Gregory Szczeszynski
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Publication number: 20210328584Abstract: Systems, methods, and apparatus for use in biasing and driving high voltage semiconductor devices using only low voltage transistors are described. The apparatus and method are adapted to control multiple high voltage semiconductor devices to enable high voltage power control, such as power amplifiers, power management and conversion (e.g. DC/DC) and other applications wherein a first voltage is large compared to the maximum voltage handling of the low voltage control transistors. According to an aspect, timing control of edges of a control signal to the high voltage semiconductor devices is provided by a basic edge delay circuit that includes a transistor, a current source and a capacitor. An inverter can be selectively coupled, via a switch, to an input and/or an output of the basic edge delay circuit to allow for timing control of a rising edge or a falling edge of the control signal.Type: ApplicationFiled: April 8, 2021Publication date: October 21, 2021Inventor: Gary Chunshien Wu
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Patent number: 10979042Abstract: Systems, methods, and apparatus for use in biasing and driving high voltage semiconductor devices using only low voltage transistors are described. The apparatus and method are adapted to control multiple high voltage semiconductor devices to enable high voltage power control, such as power amplifiers, power management and conversion (e.g. DC/DC) and other applications wherein a first voltage is large compared to the maximum voltage handling of the low voltage control transistors. According to an aspect, timing control of edges of a control signal to the high voltage semiconductor devices is provided by a basic edge delay circuit that includes a transistor, a current source and a capacitor. An inverter can be selectively coupled, via a switch, to an input and/or an output of the basic edge delay circuit to allow for timing control of a rising edge or a falling edge of the control signal.Type: GrantFiled: November 20, 2019Date of Patent: April 13, 2021Assignee: pSemi CorporationInventor: Gary Chunshien Wu
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Publication number: 20210067158Abstract: Systems, methods, and apparatus for biasing a high speed and high voltage driver using only low voltage transistors are described. The apparatus and method are adapted to control biasing voltages to the low voltage transistors such as not to exceed operating voltages of the low voltage transistors while allowing for DC to high speed operation of the driver at high voltage. A stackable and modular architecture of the driver and biasing stages is provided which can grow with a higher voltage requirement of the driver. Capacitive voltage division is used for high speed bias voltage regulation during transient phases of the driver, and resistive voltage division is used to provide bias voltage at steady state. A simpler open-drain configuration is also presented which can be used in pull-up or pull-down modes.Type: ApplicationFiled: September 15, 2020Publication date: March 4, 2021Inventor: Gary Chunshien Wu
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Patent number: 10784861Abstract: Systems, methods, and apparatus for biasing a high speed and high voltage driver using only low voltage transistors are described. The apparatus and method are adapted to control biasing voltages to the low voltage transistors such as not to exceed operating voltages of the low voltage transistors while allowing for DC to high speed operation of the driver at high voltage. A stackable and modular architecture of the driver and biasing stages is provided which can grow with a higher voltage requirement of the driver. Capacitive voltage division is used for high speed bias voltage regulation during transient phases of the driver, and resistive voltage division is used to provide bias voltage at steady state. A simpler open-drain configuration is also presented which can be used in pull-up or pull-down modes.Type: GrantFiled: November 27, 2018Date of Patent: September 22, 2020Assignee: pSemi CorporationInventor: Gary Chunshien Wu
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Patent number: 10770974Abstract: Multi-level DC-to-DC converter circuits and methods that permit a full range of output voltages, including near and at zone boundaries. Embodiments alternate among adjacent or near-by zones, operating in a first zone for a selected time and then in a second zone for a selected time. Embodiments may include a parallel capacitor voltage balancing circuit that connects a capacitor to a source voltage to charge that capacitor, or couples two or more capacitors together to transfer charge, all under the control of real-time capacitor voltage measurements. Embodiments may include a lossless voltage balancing solution where out-of-order state transitions are allowed, thus increasing or decreasing the voltage across specific capacitors to prevent voltage overstress on the converter main switches. Restrictions may be placed on the overall sequence of state transitions to reduce or avoid transition state toggling, allowing each capacitor an opportunity to have its voltage steered as necessary for balancing.Type: GrantFiled: January 16, 2019Date of Patent: September 8, 2020Assignee: pSemi CorporationInventors: Gary Chunshien Wu, David M. Giuliano, Gregory Szczeszynski
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Patent number: 10720842Abstract: Multi-level DC-to-DC converter circuits and methods that permit a full range of output voltages, including near and at zone boundaries. Embodiments alternate among adjacent or near-by zones, operating in a first zone for a selected time and then in a second zone for a selected time. Embodiments may include a parallel capacitor voltage balancing circuit that connects a capacitor to a source voltage to charge that capacitor, or couples two or more capacitors together to transfer charge, all under the control of real-time capacitor voltage measurements. Embodiments may include a lossless voltage balancing solution where out-of-order state transitions are allowed, thus increasing or decreasing the voltage across specific capacitors to prevent voltage overstress on the converter main switches. Restrictions may be placed on the overall sequence of state transitions to reduce or avoid transition state toggling, allowing each capacitor an opportunity to have its voltage steered as necessary for balancing.Type: GrantFiled: January 16, 2019Date of Patent: July 21, 2020Assignee: pSemi CorporationInventors: Gary Chunshien Wu, David M. Giuliano, Gregory Szczeszynski
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Patent number: 10720843Abstract: Multi-level DC-to-DC converter circuits and methods that permit a full range of output voltages, including near and at zone boundaries. Embodiments alternate among adjacent or near-by zones, operating in a first zone for a selected time and then in a second zone for a selected time. Embodiments may include a parallel capacitor voltage balancing circuit that connects a capacitor to a source voltage to charge that capacitor, or couples two or more capacitors together to transfer charge, all under the control of real-time capacitor voltage measurements. Embodiments may include a lossless voltage balancing solution where out-of-order state transitions are allowed, thus increasing or decreasing the voltage across specific capacitors to prevent voltage overstress on the converter main switches. Restrictions may be placed on the overall sequence of state transitions to reduce or avoid transition state toggling, allowing each capacitor an opportunity to have its voltage steered as necessary for balancing.Type: GrantFiled: January 16, 2019Date of Patent: July 21, 2020Assignee: pSemi CorporationInventors: Gary Chunshien Wu, David M. Giuliano, Gregory Szczeszynski
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Publication number: 20200228014Abstract: Multi-level DC-to-DC converter circuits and methods that permit a full range of output voltages, including near and at zone boundaries. Embodiments alternate among adjacent or near-by zones, operating in a first zone for a selected time and then in a second zone for a selected time. Embodiments may include a parallel capacitor voltage balancing circuit that connects a capacitor to a source voltage to charge that capacitor, or couples two or more capacitors together to transfer charge, all under the control of real-time capacitor voltage measurements. Embodiments may include a lossless voltage balancing solution where out-of-order state transitions are allowed, thus increasing or decreasing the voltage across specific capacitors to prevent voltage overstress on the converter main switches. Restrictions may be placed on the overall sequence of state transitions to reduce or avoid transition state toggling, allowing each capacitor an opportunity to have its voltage steered as necessary for balancing.Type: ApplicationFiled: January 16, 2019Publication date: July 16, 2020Inventors: Gary Chunshien Wu, David M. Giuliano, Gregory Szczeszynski
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Publication number: 20200228015Abstract: Multi-level DC-to-DC converter circuits and methods that permit a full range of output voltages, including near and at zone boundaries. Embodiments alternate among adjacent or near-by zones, operating in a first zone for a selected time and then in a second zone for a selected time. Embodiments may include a parallel capacitor voltage balancing circuit that connects a capacitor to a source voltage to charge that capacitor, or couples two or more capacitors together to transfer charge, all under the control of real-time capacitor voltage measurements. Embodiments may include a lossless voltage balancing solution where out-of-order state transitions are allowed, thus increasing or decreasing the voltage across specific capacitors to prevent voltage overstress on the converter main switches. Restrictions may be placed on the overall sequence of state transitions to reduce or avoid transition state toggling, allowing each capacitor an opportunity to have its voltage steered as necessary for balancing.Type: ApplicationFiled: January 16, 2019Publication date: July 16, 2020Inventors: Gary Chunshien Wu, David M. Giuliano, Gregory Szczeszynski
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Publication number: 20200228016Abstract: Multi-level DC-to-DC converter circuits and methods that permit a full range of output voltages, including near and at zone boundaries. Embodiments alternate among adjacent or near-by zones, operating in a first zone for a selected time and then in a second zone for a selected time. Embodiments may include a parallel capacitor voltage balancing circuit that connects a capacitor to a source voltage to charge that capacitor, or couples two or more capacitors together to transfer charge, all under the control of real-time capacitor voltage measurements. Embodiments may include a lossless voltage balancing solution where out-of-order state transitions are allowed, thus increasing or decreasing the voltage across specific capacitors to prevent voltage overstress on the converter main switches. Restrictions may be placed on the overall sequence of state transitions to reduce or avoid transition state toggling, allowing each capacitor an opportunity to have its voltage steered as necessary for balancing.Type: ApplicationFiled: January 16, 2019Publication date: July 16, 2020Inventors: Gary Chunshien Wu, David M. Giuliano, Gregory Szczeszynski