Patents by Inventor Gary D. Alley

Gary D. Alley has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11917950
    Abstract: A baler for hay, straw, grass, and similar feed materials is provided. The baler communicates compressed material from a vertically inclined compression passage formed in between opposing conveyer belts to a central area of a baling chamber for baling. A plunger within the baling chamber can reciprocate in two directions to form bales which are tied and discharged from both ends of the baling chamber.
    Type: Grant
    Filed: March 28, 2022
    Date of Patent: March 5, 2024
    Inventors: Jack D. Alley, James Whitaker, Gary G. Gomes
  • Patent number: 6887339
    Abstract: The invention features an RF plasma generator. The RF plasma generator includes a variable frequency RF generator, comprising an H-bridge and an RF output. The RF generator generates electromagnetic radiation having a power. The RF plasma generator further includes a matching network that includes at least one variable impedance component. The matching network also includes a first port that is electromagnetically coupled to the output of the RF generator and a second port. The RF plasma generator also includes a load that is electromagnetically coupled to the second port of the matching network, and a plasma chamber for containing a plasma having a power. The plasma chamber is electromagnetically coupled to the load and receives electromagnetic radiation having a power from the load. Adjusting at least one of the frequency of the RF generator and the variable impedance component in the matching network changes the power in the plasma.
    Type: Grant
    Filed: September 20, 2001
    Date of Patent: May 3, 2005
    Assignee: Applied Science and Technology, Inc.
    Inventors: Daniel Goodman, Andrzej Bortkiewicz, Gary D. Alley, Stephen F. Horne, William M. Holber
  • Patent number: 6320462
    Abstract: An RF amplifier includes a peak amplifier signal path, a carrier amplifier signal path and a delay line which equalizes the time delay between the peak and carrier amplifier signal paths to provide an amplifier having a relatively high power added efficiency characteristic.
    Type: Grant
    Filed: April 12, 2000
    Date of Patent: November 20, 2001
    Assignee: Raytheon Company
    Inventor: Gary D. Alley
  • Patent number: 5298787
    Abstract: A permeable base transistor (30) including a metal base layer (34) embedded in a semiconductor crystal (32) to separate collector (38) and emitter (40) regions and form a Schottky barrier with each is diclosed. The metal base layer has at least one opening (37) through which the crystal semiconductor (32) joins the collector (38) and emitter (40) regions. Ohmic contacts (42,44) are made to the emitter (38) and collector (40) regions. The width of all openings (37) in the base layer (34) is of the order of the zero bias depletion width corresponding to the carrier concentration in the opening. The thickness of the metal layer (34) is in the order of 10% of this zero bias depletion width. As a result, a potential barrier in each opening limits current flow over the lower portion of the bias range.
    Type: Grant
    Filed: April 1, 1991
    Date of Patent: March 29, 1994
    Assignee: Massachusetts Institute of Technology
    Inventors: Carl O. Bozler, Gary D. Alley, William T. Lindley, R. Allen Murphy
  • Patent number: 5032538
    Abstract: A permeable base transistor (30) including a metal base layer (34) embedded in a semiconductor crystal (32) to separate collector (38) and emitter (40) regions and form a Schottky barrier with each is disclosed. The metal base layer has at least one opening (37) through which the crystal semiconductor (32) joins the collector (38) and emitter (40) regions. Ohmic contacts (42,44) are made to the emitter (38) and collector (40) regions. The width of all openings (37) in the base layer (34) is of the order of the zero bias depletion width corresponding to the carrier concentration in the opening. The thickness of the metal layer (34) is in the order of 10% of this zero bias depletion width. As a result, a potential barrier in each opening limits current flow over the lower portion of the bias range.
    Type: Grant
    Filed: July 7, 1987
    Date of Patent: July 16, 1991
    Assignee: Massachusetts Institute of Technology
    Inventors: Carl O. Bozler, Gary D. Alley, William T. Lindley, R. Allen Murphy
  • Patent number: 4553265
    Abstract: A monolithic mixer which is impedance matched to a fundamental waveguide, utilizes a slot coupler and a coplanar transmission line to apply an RF and local oscillator signal to a Schotty-barrier diode. The dielectric substrate is utilized to create a dielectric surface wave resonance which is utilized by centering a slot coupler with respect thereto, to provide a reactive image termination at the upper sideband and thereby enhance single and double sideband mixer operation. The IF signal which is available at the output of the Schottky-barrier diode is filtered by means of an RF bypass capacitor that is located on the dielectric substrate surface.
    Type: Grant
    Filed: December 8, 1983
    Date of Patent: November 12, 1985
    Inventors: Brian J. Clifton, Gary D. Alley
  • Patent number: 4378629
    Abstract: A layer of material such as the metal base of a transistor is embedded in single crystal. A layer of the material with small, uniformly dimensioned and uniformly spaced openings is formed on a single crystal substrate, and the single crystal is grown from the exposed portions of the substrate over the layer of material. For best results, the layer of material to be embedded is deposited relative to the crystal orientation to provide a much greater rate of crystal growth laterally across the layer than away from the crystal substrate. The method is particularly useful in fabricating a permeable base transistor having slits formed in the metal base layer. An integrated circuit can be fabricated by forming a pattern of conductive material on a single crystal, that pattern having continuous regions which inhibit further crystal growth and narrow regions or regions having openings therein which permit lateral crystal growth across those regions.
    Type: Grant
    Filed: August 10, 1979
    Date of Patent: April 5, 1983
    Assignee: Massachusetts Institute of Technology
    Inventors: Carl O. Bozler, Gary D. Alley, William T. Lindley, R. Allen Murphy