Abstract: A method of grouping clock domains includes: separating a plurality of test clocks into a plurality of domain groups by adding to each respective one of the plurality of domain groups those test clocks that originate from a same clock source and have a unique clock divider ratio; sorting the domain groups in decreasing order of size; and creating a plurality of parts by adding the respective one of the plurality of domain groups to a first one of the plurality of parts in which already present test clocks have a different clock source, and creating a new part and adding the respective one of the plurality of domain groups to the new part when test clocks present in the respective one of the plurality of domain groups originate from a respective same clock source and have a different clock divider ratio as test clocks present in all previously-created parts.

Abstract: Built-in self-test (BIST) microcontroller integrated circuit adapted for logic verification. Microcontroller includes a plurality of hardware description language files representing a hierarchical description of the microcontroller, the plurality of hardware description language files including a library of circuit design elements, a plurality of library design circuit elements adapted to store a uniquely defined set of input and output signals to enable a logic BIST, and a plurality of latches adapted to store a plurality of values corresponding to a behavioral profile of a test clock.

Abstract: Built-in self-test (BIST) microcontroller integrated circuit adapted for logic verification. Microcontroller includes a plurality of hardware description language files representing a hierarchical description of the microcontroller, the plurality of hardware description language files including a library of circuit design elements, a plurality of library design circuit elements adapted to store a uniquely defined set of input and output signals to enable a logic BIST, and a plurality of latches adapted to store a plurality of values corresponding to a behavioral profile of a test clock.

Abstract: Built-in self-test (BIST) microcontroller integrated circuit adapted for logic verification. Microcontroller includes a plurality of hardware description language files representing a hierarchical description of the microcontroller, the plurality of hardware description language files including a library of circuit design elements, a plurality of library design circuit elements adapted to store a uniquely defined set of input and output signals to enable a logic BIST, and a plurality of latches adapted to store a plurality of values corresponding to a behavioral profile of a test clock.

Abstract: A method of grouping clock domains includes: separating a plurality of test clocks into a plurality of domain groups by adding to each respective one of the plurality of domain groups those test clocks that originate from a same clock source and have a unique clock divider ratio; sorting the domain groups in decreasing order of size; and creating a plurality of parts by adding the respective one of the plurality of domain groups to a first one of the plurality of parts in which already present test clocks have a different clock source, and creating a new part and adding the respective one of the plurality of domain groups to the new part when test clocks present in the respective one of the plurality of domain groups originate from a respective same clock source and have a different clock divider ratio as test clocks present in all previously-created parts.

Abstract: Disclosed are embodiments of a clock generation circuit, a design structure for the circuit and an associated method that provide deskewing functions and that further provide precise timing for both testing and functional operations. Specifically, the embodiments incorporate a deskewer circuit that is capable of receiving waveform signals from both an external waveform generator and an internal waveform generator. The external waveform generator can generate and supply to the deskewer circuit a pair of waveform signals for functional operations. The internal waveform generator can be uniquely configured with control logic and counter logic for generating and supplying a pair of waveform signals to the deskewer circuit for any one of built-in self-test (BIST) operations, macro-test operations, other test operations or functional operations.

Abstract: A system for enhancing the practicability of at-speed structural testing (ASST). In one embodiment, the system includes first means for performing statistical timing analysis on a design of logic circuitry. A second means performs a criticality analysis on the logic circuitry as a function of the statistical timing analysis so as to determine a criticality probability for each node of the logic circuitry. A third means selects nodes of the logic circuitry as a function of the criticality analysis. A fourth means selects timing paths as a function of the criticality probabilities of the selected nodes. A fifth means generates an ASST pattern for each of the selected timing paths. A sixth mean is provided to perform ASST on a fabricated instantiation of the design at functional speed using the generated ASST pattern.

Abstract: A method and circuits for testing an integrated circuit at functional clock frequency by providing a test controller generating control signals that assure proper latching of test patterns in scan chains at tester frequency and propagation of the test pattern through logic circuits being tested at functional clock frequency.

Abstract: A method and circuits for testing an integrated circuit at functional clock frequency by providing a test controller generating control signals that assure proper latching of test patterns in scan chains at tester frequency and propagation of the test pattern through logic circuits being tested at functional clock frequency.

Abstract: A method for automatically generating test patterns for digital logic circuitry using an automatic test pattern generation tool. The method includes generating test patterns and applying faulty behavior to various paths within the digital logic circuitry. As each circuit path is tested, tested circuit nodes along the circuit path are marked as “exercised.” Subsequent test paths are assembled by avoiding marked circuit nodes. In this manner, coverage of paths tested may be increased and many circuit nodes can be tested efficiently.

Abstract: A method and system of identifying sequential functional paths for IC testing methods are disclosed. In one embodiment, a method may include a method of sequential functional path identification for at-speed structural test, the method comprising: using a timing tool to enumerate a plurality of critical paths in a circuit; identifying which of the plurality of critical paths are sequential functional paths that will function during functional operation of the IC by identifying which of the plurality of critical paths a test can be generated for using a test sequence having n functional capture cycles, where n is greater than 2; performing path test generation for the sequential functional paths using launch-off-scan test sequences; and performing path test generation for critical paths not tested by the launch-of-scan test sequences, using launch-off-capture test sequences having two functional captures.

Abstract: A design structure embodied in a machine readable medium used in a design process includes an apparatus for testing logic devices configured across asynchronous clock domains, including a deactivation mechanism for deactivating, during at-speed fault testing, a local clock signal for each of a first plurality of latches having at least one data input thereto originating from a source located within an asynchronous clock domain with respect thereto; wherein the deactivation mechanism is configured to permit data capture within the first plurality of latches, and wherein the deactivation mechanism is further configured to permit at-speed data launch from the first plurality of latches to downstream latches with respect thereto during at-speed testing.

Abstract: An apparatus for selectively implementing launch-off-scan capability in at-speed testing of integrated circuit devices includes a control device configured to selectively disable a master clock signal of a latch structure under test such that a pulse sequence of a system clock signal results in a slave-master-slave clock pulse sequence in the latch structure under test; wherein the control device utilizes the system clock signal as an input thereto and operates in a self-resetting fashion that is timing independent with respect to a scan chain.

Abstract: A method and circuits for testing an integrated circuit at functional clock frequency by providing a test controller generating control signals that assure proper latching of test patterns in scan chains at tester frequency and propagation of the test pattern through logic circuits being tested at functional clock frequency.

Abstract: A method and circuits for testing an integrated circuit at functional clock frequency by providing a test controller generating control signals that assure proper latching of test patterns in scan chains at tester frequency and propagation of the test pattern through logic circuits being tested at functional clock frequency.

Abstract: A method for testing logic devices configured across asynchronous clock domains includes deactivating, during at-speed fault testing, a local clock signal for each of a first plurality of latches having at least one data input thereto originating from a source located within an asynchronous clock domain with respect thereto. The deactivation of a local clock signal for each of the plurality of latches is implemented in a manner so as to permit data capture within the first plurality of latches, and wherein the deactivation of a local clock signal for each of the plurality of latches is further implemented in a manner so as to permit at-speed data launch therefrom to downstream latches with respect thereto during at-speed testing.

Abstract: Methods, systems and program products for evaluating an IC chip are disclosed. In one embodiment, the method includes running a statistical static timing analysis (SSTA) of a full IC chip design; creating at-functional-speed test (AFST) robust paths for an IC chip, the created robust paths representing a non-comprehensive list of AFST robust paths for the IC chip; and re-running the SSTA with the SSTA delay model setup based on the created robust paths. A process coverage is calculated for evaluation from the SSTA runnings; and a particular IC chip is evaluated based on the process coverage.

Abstract: Disclosed are embodiments of a clock generation circuit, a design structure for the circuit and an associated method that provide deskewing functions and that further provide precise timing for both testing and functional operations. Specifically, the embodiments incorporate a deskewer circuit that is capable of receiving waveform signals from both an external waveform generator and an internal waveform generator. The external waveform generator can generate and supply to the deskewer circuit a pair of waveform signals for functional operations. The internal waveform generator can be uniquely configured with control logic and counter logic for generating and supplying a pair of waveform signals to the deskewer circuit for any one of built-in self-test (BIST) operations, macro-test operations, other test operations or functional operations.

Abstract: A method and system of identifying sequential functional paths for IC testing methods are disclosed. In one embodiment, a method may include a method of sequential functional path identification for at-speed structural test, the method comprising: using a timing tool to enumerate a plurality of critical paths in a circuit; identifying which of the plurality of critical paths are sequential functional paths that will function during functional operation of the IC by identifying which of the plurality of critical paths a test can be generated for using a test sequence having n functional capture cycles, where n is greater than 2; performing path test generation for the sequential functional paths using launch-off-scan test sequences; and performing path test generation for critical paths not tested by the launch-of-scan test sequences, using launch-off-capture test sequences having two functional captures.

Abstract: A system for enhancing the practicability of at-speed structural testing (ASST). In one embodiment, the system includes first means for performing statistical timing analysis on a design of logic circuitry. A second means performs a criticality analysis on the logic circuitry as a function of the statistical timing analysis so as to determine a criticality probability for each node of the logic circuitry. A third means selects nodes of the logic circuitry as a function of the criticality analysis. A fourth means selects timing paths as a function of the criticality probabilities of the selected nodes. A fifth means generates an ASST pattern for each of the selected timing paths. A sixth mean is provided to perform ASST on a fabricated instantiation of the design at functional speed using the generated ASST pattern.