Abstract: Encachement apparatus consisting of first and second caches responsive to first and second keys, respectively, for outputting first and second data therefrom. In one embodiment, the second cache which includes a stack having a plurality of frames, outputs data contained in a current frame thereof in response to a second key which is obtained from the first cache. The data outputted from each cache is received substantially simultaneously at a combiner which combines such data to produce the desired third data from the dual cache system.

Abstract: Encachement apparatus consisting of a first cache, a second cache connected to the first cache, registers for storing data, an adder receiving inputs from a first multiplexer connected to the first cache and a second multiplexer connected to the second cache and to the registers, and control apparatus connected to the first cache, the first multiplexer, and the second multiplexer. The first cache outputs a cache entry in response to a key. The cache entry contains a first displacement value, a base specifier specifying either one of the registers or the second cache, and in the case of entries specifying the second cache, a second displacement value. The first displacement value is output to the first multiplexer, the base specifier is output to the control apparatus, and the second displacement, if present, is output to the second cache.

Abstract: Encachement apparatus consisting of a first cache, a second cache connected to the first cache, registers for storing data, an adder receiving inputs from a first multiplexer connected to the first cache and a second multiplexer connected to the second cache and to the registers, and control apparatus connected to the first cache, the first multiplexer, and the second multiplexer. The first cache outputs a cache entry in response to a key. The cache entry contains a first displacement value, a base specifier specifying either one of the registers or the second cache, and in the case of entries specifying the second cache, a second displacement value. The first displacement value is output to the first multiplexer, the base specifier is output to the control apparatus, and the second displacement, if present, is output to the second cache.

Abstract: Improved apparatus for specifying and computing the current length of varying-length data items, together with methods for computing the current length. The apparatus and methods are used in a digital computer system wherein data items are represented by names associated with name table entry items in memory. The name table entry associated with the name represented by the varying-length data item includes a current number of elements item specifier specifying the address of a current number of elements item which specifies the number of elements currently in the represented varying-length data item. The name table entry further includes an element size specifier specifying the size of the elements. A name processor in the processor uses the current number of elements item specifier to obtain the the address of the current number of elements item and and fetches the current number of elements item from memory.

Abstract: Improved apparatus for specifying and resolving addresses of operands in a digital data processing system. Instructions executed by the system are contained in procedures. Addresses are calculated using a set of architectural base addresses. Operands are represented in the instructions by means of names. The names include immediate names, which directly specify one of the architectural base registers and a displacement, and table names, which specify a name table entry in a name table associated with the procedure. The name table entry specifies how the address of the operand represented by the table name may be derived using the architectural base addresses and information contained in the name table. Each name table entry includes a basic name table entry. The basic name table entry contains a base source specifier and a base or displacement specifier.