Abstract: A method and system for managing peripheral connection wakeup signaling in a processing system supporting multiple virtual machines provides a mechanism by which ownership of a peripheral having system wakeup capability is transferred between virtual machines. The power management event signal is connected to a service processor input that in turn signals a hypervisor to direct the wakeup activity to a particular logical partition in which the virtual machine was last executing. The hypervisor can then determine whether or not to wake up the entire system, or portions thereof and can direct the power management event to the appropriate virtual machine. In particular the peripheral may be an Ethernet adapter supporting Wake-On-LAN capability. State initialization, which is typically ensured by system power cycling is provided instead by controlling power to the standby power source or in some instances by forcing an indication of a disconnect/reconnect of the wakeup signaling connection.

Abstract: A method and system for managing peripheral connection wakeup signaling in a processing system supporting multiple virtual machines provides a mechanism by which ownership of a peripheral having system wakeup capability is transferred between virtual machines. The power management event signal is connected to a service processor input that in turn signals a hypervisor to direct the wakeup activity to a particular logical partition in which the virtual machine was last executing. The hypervisor can then determine whether or not to wake up the entire system, or portions thereof and can direct the power management event to the appropriate virtual machine. In particular the peripheral may be an Ethernet adapter supporting Wake-On-LAN capability. State initialization, which is typically ensured by system power cycling is provided instead by controlling power to the standby power source or in some instances by forcing an indication of a disconnect/reconnect of the wakeup signaling connection.

Abstract: A system and method for fast system recovery that bypasses diagnostic routines by disconnecting failed hardware from the system before rebooting. Failed hardware and hardware that will be affected by removal of the failed hardware of the system are disconnected from the system. The system is restarted, and because the failed hardware is disconnected, diagnostic routines may safely be eliminated from the reboot process.

Abstract: In response to the start of an initialization sequence at a service processor, if power to a main processor was interrupted at a most-recent time that an operating system executed on the main processor, power to the main processor is turned on, the operating system is started executing on the main processor, data from the non-volatile memory of the service processor is provided to the operating system, and the service processor is reset, which restarts the initialization sequence. If the power to the main processor was not interrupted at the most-recent time that the operating system executed on the main processor, and if the operating system is currently executing on the main processor, a monitoring function is started in the service processor, which monitors for errors at a computer system.

Abstract: The aspects of the present invention provide a computer implemented method, an apparatus, and a computer usable program code for identifying a service processor with current setting information. First stored information for a service processor is retrieved from a first memory in the first service processor. Second stored information for the service processor is retrieved from a second memory in a data processing system to which the service processor is connected. The first stored information is compared with the second stored information to form a comparison as to whether the service processor was previously connected to the data processing system and to determine whether the service processor was a last service processor to fully communicate with system firmware in the data processing system. The service processor has current setting information if the service processor was previously connected to the data processing system and was the last service processor to fully communicate with the system firmware.

Abstract: A system and method for fast system recovery that bypasses diagnostic routines by disconnecting failed hardware from the system before rebooting. Failed hardware and hardware that will be affected by removal of the failed hardware of the system are disconnected from the system. The system is restarted, and because the failed hardware is disconnected, diagnostic routines may safely be eliminated from the reboot process.

Abstract: A method and system for managing peripheral connection wakeup signaling in a processing system supporting multiple virtual machines provides a mechanism by which ownership of a peripheral having system wakeup capability is transferred between virtual machines. The power management event signal is connected to a service processor input that in turn signals a hypervisor to direct the wakeup activity to a particular logical partition in which the virtual machine was last executing. The hypervisor can then determine whether or not to wake up the entire system, or portions thereof and can direct the power management event to the appropriate virtual machine. In particular the peripheral may be an Ethernet adapter supporting Wake-On-LAN capability. State initialization, which is typically ensured by system power cycling is provided instead by controlling power to the standby power source or in some instances by forcing an indication of a disconnect/reconnect of the wakeup signaling connection.

Abstract: A system and method for fast system recovery that bypasses diagnostic routines by disconnecting failed hardware from the system before rebooting. Failed hardware and hardware that will be affected by removal of the failed hardware of the system are disconnected from the system. The system is restarted, and because the failed hardware is disconnected, diagnostic routines may safely be eliminated from the reboot process.

Abstract: A method, apparatus, and computer instructions for managing a set of I/O subsystems. Previously stored I/O subsystem information is compared to current I/O subsystem information collected from the set of I/O subsystems. The I/O subsystem information includes addresses associated with unique identifiers. Information in the set of subsystems is recorrelated if a mismatch is present between the previously stored I/O subsystem information and the current I/O subsystem information in the set of subsystems.

Abstract: A method and system for managing peripheral connection wakeup signaling in a processing system supporting multiple virtual machines provides a mechanism by which ownership of a peripheral having system wakeup capability is transferred between virtual machines. The power management event signal is connected to a service processor input that in turn signals a hypervisor to direct the wakeup activity to a particular logical partition in which the virtual machine was last executing. The hypervisor can then determine whether or not to wake up the entire system, or portions thereof and can direct the power management event to the appropriate virtual machine. In particular the peripheral may be an Ethernet adapter supporting Wake-On-LAN capability. State initialization, which is typically ensured by system power cycling is provided instead by controlling power to the standby power source or in some instances by forcing an indication of a disconnect/reconnect of the wakeup signaling connection.

Abstract: In response to the start of an initialization sequence at a service processor, if power to a main processor was interrupted at a most-recent time that an operating system executed on the main processor, power to the main processor is turned on, the operating system is started executing on the main processor, data from the non-volatile memory of the service processor is provided to the operating system, and the service processor is reset, which restarts the initialization sequence. If the power to the main processor was not interrupted at the most-recent time that the operating system executed on the main processor, and if the operating system is currently executing on the main processor, a monitoring function is started in the service processor, which monitors for errors at a computer system.

Abstract: The present invention provides a method and computer program product for reading an encoded cable speed/length value contained within an interconnection cable to set the interconnection speed of two or more components connected by the interconnection cable within a computing environment. This method detects changes to the cable connections within the I/O fabric of the computing environment, and autonomically reconfigures the connected components to enable the interconnected devices to communicate at the maximum effective bandwidth, based on the length of the interconnection cables utilized.

Abstract: A method, apparatus and computer program product are provided for implementing time synchronization correction in computer systems. A service processor includes a battery-backed hardware clock, and a hypervisor includes a hypervisor system clock. A common timer resource is accessible by the hypervisor and the service processor. To synchronize the battery-backed hardware clock and the hypervisor system clock, the common timer resource is used to measure the latency in the communication medium between the hypervisor and the service processor. The latency is then added onto the time value received in time of day messages between the hypervisor and the service processor for time synchronization correction in the computer systems.

Abstract: A method, apparatus and computer program product are provided for implementing time synchronization correction in computer systems. A service processor includes a battery-backed hardware clock, and a hypervisor includes a hypervisor system clock. A common timer resource is accessible by the hypervisor and the service processor. To synchronize the battery-backed hardware clock and the hypervisor system clock, the common timer resource is used to measure the latency in the communication medium between the hypervisor and the service processor. The latency is then added onto the time value received in time of day messages between the hypervisor and the service processor for time synchronization correction in the computer systems.

Abstract: A method, apparatus, and computer instructions for managing a set of I/O subsystems. Previously stored I/O subsystem information is compared to current I/O subsystem information collected from the set of I/O subsystems. The I/O subsystem information includes addresses associated with unique identifiers. Information in the set of subsystems is recorrelated if a mismatch is present between the previously stored I/O subsystem information and the current I/O subsystem information in the set of subsystems.

Abstract: A method and apparatus for improving direct memory access and cache performance utilizing a special Input/Output or “I/O” page, defined as having a large size (e.g., 4 Kilobytes or 4 Kb), but with distinctive cache line characteristics. For Direct Memory Access (DMA) reads, the first cache line in the I/O page may be accessed, by a Peripheral Component Interconnect (PCI) Host Bridge, as a cacheable read and all other lines are non-cacheable access (DMA Read with no intent to cache). For DMA writes, the PCI Host Bridge accesses all cache lines as cacheable. The PCI Host Bridge maintains a cache snoop granularity of the I/O page size for data, which means that if the Host Bridge detects a store (invalidate) type system bus operation on any cache line within an I/O page, cached data within that page is invalidated, the Level 1 and Level 2 ((L1/L2) caches continue to treat all cache lines in this page as cacheable).