Abstract: An exemplary method includes solving on a computing system an optimal power flow formulation for a plurality of generators in a power system. The solving includes computing using multi-threaded parallelism a plurality of constraints for the formulation, computing using multi-threaded parallelism a plurality of Jacobian functions of the constraints, and computing using multi-threaded parallelism a Hessian of Lagrangian functions. The method further includes outputting results of the solving, wherein the results comprise values of generation levels for the plurality of generators. Apparatus and program products are also disclosed.

Abstract: An exemplary method includes solving on a computing system an optimal power flow formulation for a plurality of generators in a power system. The solving includes computing using multi-threaded parallelism a plurality of constraints for the formulation, computing using multi-threaded parallelism a plurality of Jacobian functions of the constraints, and computing using multi-threaded parallelism a Hessian of Lagrangian functions. The method further includes outputting results of the solving, wherein the results comprise values of generation levels for the plurality of generators. Apparatus and program products are also disclosed.

Abstract: An exemplary method includes solving on a computing system an optimal power flow formulation for a plurality of generators in a power system. The solving includes computing using multi-threaded parallelism a plurality of constraints for the formulation, computing using multi-threaded parallelism a plurality of Jacobian functions of the constraints, and computing using multi-threaded parallelism a Hessian of Lagrangian functions. The method further includes outputting results of the solving, wherein the results comprise values of generation levels for the plurality of generators. Apparatus and program products are also disclosed.

Abstract: An exemplary method includes solving on a computing system an optimal power flow formulation for a plurality of generators in a power system. The solving includes computing using multi-threaded parallelism a plurality of constraints for the formulation, computing using multi-threaded parallelism a plurality of Jacobian functions of the constraints, and computing using multi-threaded parallelism a Hessian of Lagrangian functions. The method further includes outputting results of the solving, wherein the results comprise values of generation levels for the plurality of generators. Apparatus and program products are also disclosed.

Abstract: An exemplary method includes solving on a computing system an optimal power flow formulation for a plurality of generators in a power system. The solving includes computing using multi-threaded parallelism a plurality of constraints for the formulation, computing using multi-threaded parallelism a plurality of Jacobian functions of the constraints, and computing using multi-threaded parallelism a Hessian of Lagrangian functions. The method further includes outputting results of the solving, wherein the results comprise values of generation levels for the plurality of generators. Apparatus and program products are also disclosed.

Abstract: An exemplary method includes solving on a computing system an optimal power flow formulation for a plurality of generators in a power system. The solving includes computing using multi-threaded parallelism a plurality of constraints for the formulation, computing using multi-threaded parallelism a plurality of Jacobian functions of the constraints, and computing using multi-threaded parallelism a Hessian of Lagrangian functions. The method further includes outputting results of the solving, wherein the results comprise values of generation levels for the plurality of generators. Apparatus and program products are also disclosed.

Abstract: An exemplary method includes solving on a computing system an optimal power flow formulation for a plurality of generators in a power system. The solving includes computing using multi-threaded parallelism a plurality of constraints for the formulation, computing using multi-threaded parallelism a plurality of Jacobian functions of the constraints, and computing using multi-threaded parallelism a Hessian of Lagrangian functions. The method further includes outputting results of the solving, wherein the results comprise values of generation levels for the plurality of generators. Apparatus and program products are also disclosed.

Abstract: An exemplary method includes solving on a computing system an optimal power flow formulation for a plurality of generators in a power system. The solving includes computing using multi-threaded parallelism a plurality of constraints for the formulation, computing using multi-threaded parallelism a plurality of Jacobian functions of the constraints,and computing using multi-threaded parallelism a Hessian of Lagrangian functions. The method further includes outputting results of the solving, wherein the results comprise values of generation levels for the plurality of generators. Apparatus and program products are also disclosed.

Abstract: An embodiment of the invention provides a method of separating an early clock pulse and a late clock pulse into two different latches, wherein the early clock pulse is generated through a bit line. In response to the early clock pulse rising, a first data waveform is sent to a fourth data waveform. In response to a third data waveform rising, an early precharge is turned off. In response to the turning off of the early precharge and in response to a fifth data waveform dropping, an eighth data waveform rises if the first data waveform has a value of 1. In response to a sixth data waveform rising, a first pulse latch is opened.

Abstract: An embodiment of the invention provides a method of separating an early clock pulse and a late clock pulse into two different latches, wherein the early clock pulse is generated through a bit line. In response to the early clock pulse rising, a first data waveform is sent to a fourth data waveform. In response to a third data waveform rising, an early precharge is turned off. In response to the turning off of the early precharge and in response to a fifth data waveform dropping, an eighth data waveform rises if the first data waveform has a value of 1.

Abstract: A method and structure for determining a listing of host processors on a network to perform a parallel application, including determining a listing of all possible hosts on the network for performing the parallel application, determining for each of the possible hosts a current capacity and a current utilization, calculating for each of the possible hosts a difference between the current capacity and the current utilization, and selecting from the listing of all possible hosts a listing of hosts based on sorting the calculated differences.

Abstract: A method and structure for determining a listing of host processors on a network to perform a parallel application, including determining a listing of all possible hosts on the network for performing the parallel application, determining for each of the possible hosts a current capacity and a current utilization, calculating for each of the possible hosts a difference between the current capacity and the current utilization, and selecting from the listing of all possible hosts a listing of hosts based on sorting the calculated differences.

Abstract: A method and structure for determining a listing of host processors on a network to perform a parallel application, including determining a listing of all possible hosts on the network for performing the parallel application, determining for each of the possible hosts a current capacity and a current utilization, calculating for each of the possible hosts a difference between the current capacity and the current utilization, and selecting from the listing of all possible hosts a listing of hosts based on sorting the calculated differences.

Abstract: A method and structure for determining a listing of host processors on a network to perform a parallel application, including determining a listing of all possible hosts on the network for performing the parallel application, determining for each of the possible hosts a current capacity and a current utilization, calculating for each of the possible hosts a difference between the current capacity and the current utilization, and selecting from the listing of all possible hosts a listing of hosts based on sorting the calculated differences.

Abstract: A method and structure for determining a listing of host processors on a network to perform a parallel application, including determining a listing of all possible hosts on the network for performing the parallel application, determining for each of the possible hosts a current capacity and a current utilization, calculating for each of the possible hosts a difference between the current capacity and the current utilization, and selecting from the listing of all possible hosts a listing of hosts based on sorting the calculated differences.

Abstract: A method, multi-computer media and apparatus that uses an economics model to manage the demand and the resource satisfying that demand for multi-computer memory. The present invention quantifies demand as a function of space, and computer resource as a function of time, so that a computational system can meet an application demand.

Abstract: A circuit design method, computer program product and chip design system embodying the method. A gate selected for static timing analysis (STA) from a circuit design. Initial performance characteristics (e.g., load and transition slew) are determined for the selected gate. A charge equivalent effective capacitance (CQeff) is determined for the gate from the initial performance characteristics. A gate delay is determined in a single pass for the gate using CQeff as an effective load for said selected gate. Optionally, if the total gate load capacitance (Ctot) exceeds CQeff by less than a minimum, the effective capacitance (Ceff) is determined and used for determining the gate delay instead.

Abstract: Disclosed is a method and structure that partitions an integrated circuit design by identifying logical blocks within the integrated circuit design based on size heuristics of logical macros in the design hierarchy. The invention determines whether the number of logical blocks is within a range of desired number of logical blocks and repeats the process of identifying logical blocks for different hierarchical levels of the integrated circuit design until the number of logical blocks is within the range of the desired number of logical blocks. This serves as a guide to partition the chip as opposed to a grid-like partitioning.

Abstract: A method, multi-computer media and apparatus that uses an economics model to manage the demand and the resource satisfying that demand for multi-computer memory. The present invention quantifies demand as a function of space, and computer resource as a function of time, so that a computational system can meet an application demand.

Abstract: A method and structure for determining a listing of host processors on a network to perform a parallel application, including determining a listing of all possible hosts on the network for performing the parallel application, determining for each of the possible hosts a current capacity and a current utilization, calculating for each of the possible hosts a difference between the current capacity and the current utilization, and selecting from the listing of all possible hosts a listing of hosts based on sorting the calculated differences.