Abstract: A nanoimprint lithography method includes contacting a composite polymerizable coating formed from a pretreatment composition and an imprint resist with a nanoimprint lithography template defining recesses. The composite polymerizable coating is polymerized to yield a composite polymeric layer defining a pre-etch plurality of protrusions corresponding to the recesses of the nanoimprint lithography template. The nanoimprint lithography template is separated from the composite polymeric layer. At least one of the pre-etch plurality of protrusions corresponds to a boundary between two of the discrete portions of the imprint resist, and the pre-etch plurality of protrusions have a variation in pre-etch height of ±10% of a pre-etch average height. The pre-etch plurality of protrusions is etched to yield a post-etch plurality of protrusions having a variation in post-etch height of ±10% of a post-etch average height, and the pre-etch average height exceeds the post-etch average height.

Abstract: A nanoimprint lithography method includes contacting a composite polymerizable coating formed from a pretreatment composition and an imprint resist with a nanoimprint lithography template defining recesses. The composite polymerizable coating is polymerized to yield a composite polymeric layer defining a pre-etch plurality of protrusions corresponding to the recesses of the nanoimprint lithography template. The nanoimprint lithography template is separated from the composite polymeric layer. At least one of the pre-etch plurality of protrusions corresponds to a boundary between two of the discrete portions of the imprint resist, and the pre-etch plurality of protrusions have a variation in pre-etch height of ±10% of a pre-etch average height. The pre-etch plurality of protrusions is etched to yield a post-etch plurality of protrusions having a variation in post-etch height of ±10% of a post-etch average height, and the pre-etch average height exceeds the post-etch average height.

Abstract: A nanoimprint lithography method includes contacting a composite polymerizable coating formed from a pretreatment composition and an imprint resist with a nanoimprint lithography template defining recesses. The composite polymerizable coating is polymerized to yield a composite polymeric layer defining a pre-etch plurality of protrusions corresponding to the recesses of the nanoimprint lithography template. The nanoimprint lithography template is separated from the composite polymeric layer. At least one of the pre-etch plurality of protrusions corresponds to a boundary between two of the discrete portions of the imprint resist, and the pre-etch plurality of protrusions have a variation in pre-etch height of ±10% of a pre-etch average height. The pre-etch plurality of protrusions is etched to yield a post-etch plurality of protrusions having a variation in post-etch height of ±10% of a post-etch average height, and the pre-etch average height exceeds the post-etch average height.

Abstract: Disclosed is an integrated circuit comprising a plurality of cores attached to at least one transmitter and receiver, an optical transmission network embedded within the wire levels of the integrated circuit, and wherein the transmitter and receivers send and receive data on the network. Also disclosed is a method of transmitting signals within an integrated circuit comprising an integrated circuit comprising a plurality of cores and optical paths, selecting an optical path from the plurality of optical paths for transmitting data, and transmitting the data on the selected optical path. Also disclosed is an integrated circuit comprising an optical transmission network, a plurality of cores, and a plurality of controllers, all three being operatively attached to each other.

Abstract: A method for automatically wiring (i.e., routing) an integrated circuit chip after completing the placement of cells on the chip is described. The method employs a maze routing such that the spacing between the routed wires is increased, while at the same time maintaining control over the total wiring length. The maze routing herein described is modified to improve chip yield, reduce wiring capacitance, limit power consumption and coupled signal noise, all of which are achieved by increasing wire-to-wire spacings.