Abstract: Methods and apparatus of bioreactors for therapeutic cells manufacturing are provided herein. In some embodiments, a bioreactor includes: an upper bioreactor reservoir configured to perform multiple cell therapy manufacturing process steps including genetic modification and expansion to a plurality of cells disposed therein, wherein the upper bioreactor reservoir includes a plurality of ports for delivering fluids into and out of the upper bioreactor reservoir; a lower bioreactor compartment configured to hold a suspension comprising a molecular species; and a membrane disposed between the lower bioreactor compartment and the upper bioreactor reservoir, wherein the membrane includes a plurality of micro-straws extending through the membrane and into the upper bioreactor reservoir to transfect the plurality of cells with the molecular species.

Abstract: The present disclosure relates to semiconductor core assemblies and methods of forming the same. The semiconductor core assemblies described herein may be utilized to form semiconductor package assemblies, printed circuit board (PCB) assemblies, PCB spacer assemblies, chip carrier assemblies, intermediate carrier assemblies (e.g., for graphics cards), and the like. In one embodiment, a substrate core (e.g., a core structure) is implanted with dopants to achieve a desired bulk resistivity or conductivity. One or more conductive interconnections are formed in the substrate core and one or more redistribution layers are formed on surfaces thereof. The substrate core may thereafter be utilized as a core structure for a semiconductor package, PCB, PCB spacer, chip carrier, intermediate carrier, or the like.

Abstract: Methods and apparatus of bioreactors for therapeutic cells manufacturing are provided herein. In some embodiments, a bioreactor includes: an upper bioreactor reservoir configured to perform multiple cell therapy manufacturing process steps including genetic modification and expansion to a plurality of cells disposed therein, wherein the upper bioreactor reservoir includes a plurality of ports for delivering fluids into and out of the upper bioreactor reservoir; a lower bioreactor compartment configured to hold a suspension comprising a molecular species; and a membrane disposed between the lower bioreactor compartment and the upper bioreactor reservoir, wherein the membrane includes a plurality of micro-straws extending through the membrane and into the upper bioreactor reservoir to transfect the plurality of cells with the molecular species.

Abstract: Embodiments of the present disclosure relate to an apparatus and a method for reducing the adverse effects of exposing portions of an integrated circuit (IC) device to various forms of radiation during one or more operations found within the IC formation processing sequence by controlling the environment surrounding and temperature of an IC device during one or more parts of the IC formation processing sequence. The provided energy may include the delivery of radiation to a surface of a formed or a partially formed IC device during a deposition, etching, inspection or post-processing process operation. In some embodiments of the disclosure, the temperature of the substrate on which the IC device is formed is controlled to a temperature that is below room temperature (e.g., <20° C.) during the one or more parts of the IC formation processing sequence.

Abstract: Embodiments of the present disclosure relate to precision material modification of three dimensional (3D) features or advanced processing techniques. Directional ion implantation methods are utilized to selectively modify desired regions of a material layer to improve etch characteristics of the modified material. For example, a modified region of a material layer may exhibit improved etch selectivity relative to an unmodified region of the material layer. Methods described herein are useful for manufacturing 3D hardmasks which may be advantageously utilized in various integration schemes, such as fin isolation and gate-all-around, among others. Multiple directional ion implantation processes may also be utilized to form dopant gradient profiles within a modified layer to further influence etching processes.

Abstract: Embodiments of the present disclosure relate to an apparatus and a method for reducing the adverse effects of exposing portions of an integrated circuit (IC) device to various forms of radiation during one or more operations found within the IC formation processing sequence by controlling the environment surrounding and temperature of an IC device during one or more parts of the IC formation processing sequence. The provided energy may include the delivery of radiation to a surface of a formed or a partially formed IC device during a deposition, etching, inspection or post-processing process operation. In some embodiments of the disclosure, the temperature of the substrate on which the IC device is formed is controlled to a temperature that is below room temperature (e.g., <20° C.) during the one or more parts of the IC formation processing sequence.

Abstract: Embodiments of the present disclosure relate to precision material modification of three dimensional (3D) features or advanced processing techniques. Directional ion implantation methods are utilized to selectively modify desired regions of a material layer to improve etch characteristics of the modified material. For example, a modified region of a material layer may exhibit improved etch selectivity relative to an unmodified region of the material layer. Methods described herein are useful for manufacturing 3D hardmasks which may be advantageously utilized in various integration schemes, such as fin isolation and gate-all-around, among others. Multiple directional ion implantation processes may also be utilized to form dopant gradient profiles within a modified layer to further influence etching processes.

Abstract: Embodiments of the present disclosure relate to an apparatus and a method for reducing the adverse effects of exposing portions of an integrated circuit (IC) device to various forms of radiation during one or more operations found within the IC formation processing sequence by controlling the environment surrounding and temperature of an IC device during one or more parts of the IC formation processing sequence. The provided energy may include the delivery of radiation to a surface of a formed or a partially formed IC device during a deposition, etching, inspection or post-processing process operation. In some embodiments of the disclosure, the temperature of the substrate on which the IC device is formed is controlled to a temperature that is below room temperature (e.g., <20° C.) during the one or more parts of the IC formation processing sequence.

Abstract: Embodiments of the present disclosure relate to precision material modification of three dimensional (3D) features or advanced processing techniques. Directional ion implantation methods are utilized to selectively modify desired regions of a material layer to improve etch characteristics of the modified material. For example, a modified region of a material layer may exhibit improved etch selectivity relative to an unmodified region of the material layer. Methods described herein are useful for manufacturing 3D hardmasks which may be advantageously utilized in various integration schemes, such as fin isolation and gate-all-around, among others. Multiple directional ion implantation processes may also be utilized to form dopant gradient profiles within a modified layer to further influence etching processes.

Abstract: Embodiments of the present disclosure relate to an apparatus and a method for reducing the adverse effects of exposing portions of an integrated circuit (IC) device to various forms of radiation during one or more operations found within the IC formation processing sequence by controlling the environment surrounding and temperature of an IC device during one or more parts of the IC formation processing sequence. The provided energy may include the delivery of radiation to a surface of a formed or a partially formed IC device during a deposition, etching, inspection or post-processing process operation. In some embodiments of the disclosure, the temperature of the substrate on which the IC device is formed is controlled to a temperature that is below room temperature (e.g., <20° C.) during the one or more parts of the IC formation processing sequence.

Abstract: Embodiments of the present disclosure relate to precision material modification of three dimensional (3D) features or advanced processing techniques. Directional ion implantation methods are utilized to selectively modify desired regions of a material layer to improve etch characteristics of the modified material. For example, a modified region of a material layer may exhibit improved etch selectivity relative to an unmodified region of the material layer. Methods described herein are useful for manufacturing 3D hardmasks which may be advantageously utilized in various integration schemes, such as fin isolation and gate-all-around, among others. Multiple directional ion implantation processes may also be utilized to form dopant gradient profiles within a modified layer to further influence etching processes.

Abstract: Embodiments of the disclosure provide apparatus and methods for modifying a surface of a substrate using a plasma modification process. In one embodiment, a process generally includes the removal and/or redistribution of a portion of an exposed surface of the substrate by use of an energetic particle beam while the substrate is disposed within a particle beam modification apparatus. Embodiments may also provide a plasma modification process that includes one or more pre-planarization processing steps and/or one or more post-planarization processing steps that are all performed within one processing system. Some embodiments may provide an apparatus and methods for planarizing a surface of a substrate by performing all of the plasma modification processes within either the same processing chamber, the same processing system or within processing chambers found in two or more processing systems.

Abstract: A superconducting fault current limiter recovery system includes a superconducting fault current limiter, a shunt electrically coupled in parallel with the superconducting fault current limiter, and a bypass path also electrically coupled in parallel with the superconducting fault current limiter. The bypass path enables a load current to flow through the bypass path during a bypass condition. Thus, load current may be quickly reestablished to serve loads after a fault condition via the bypass path while a superconductor of the superconductor fault current limiter has time to return to a superconducting state after the fault condition.

Abstract: A first species is implanted into an entire surface of a workpiece and helium is implanted into this entire surface with a non-uniform dose. The first species may be, for example, hydrogen, helium, or nitrogen. The helium has a higher dose at a portion of a periphery of the workpiece. When the workpiece is split, this split is initiated at the periphery with the higher dose. The non-uniform dose may be formed by altering a scan speed of the workpiece or an ion beam current of the helium. In one instance, the non-uniform dose of the helium is larger than a uniform dose of the hydrogen.

Abstract: A superconducting fault current limiter recovery system includes a superconducting fault current limiter, a shunt electrically coupled in parallel with the superconducting fault current limiter, and a bypass path also electrically coupled in parallel with the superconducting fault current limiter. The bypass path enables a load current to flow through the bypass path during a bypass condition. Thus, load current may be quickly reestablished to serve loads after a fault condition via the bypass path while a superconductor of the superconductor fault current limiter has time to return to a superconducting state after the fault condition.

Abstract: A first species is implanted into an entire surface of a workpiece and helium is implanted into this entire surface with a non-uniform dose. The first species may be, for example, hydrogen, helium, or nitrogen. The helium has a higher dose at a portion of a periphery of the workpiece. When the workpiece is split, this split is initiated at the periphery with the higher dose. The non-uniform dose may be formed by altering a scan speed of the workpiece or an ion beam current of the helium. In one instance, the non-uniform dose of the helium is larger than a uniform dose of the hydrogen.

Abstract: Techniques for atomic layer deposition (ALD) are disclosed. In one particular exemplary embodiment, the techniques may be realized as a system for ALD comprising a plurality of reactors in a stacked configuration, wherein each reactor comprises a wafer holding portion for holding a target wafer, a gas assembly coupled to the plurality of reactors and configured to provide at least one gas to at least one of the plurality of reactors, and an exhaust assembly coupled to the plurality of reactors and configured to exhaust the at least one gas from the at least one of the plurality of reactors. The gas assembly may further comprise a valve assembly coupled to each of the first gas inlet, the second gas inlet, and the third gas inlet, where the valve assembly is configured to selectively release at least one of the first gas, the second gas, and the third gas.

Abstract: Techniques for cold implantation of carbon-containing species are disclosed. In one particular exemplary embodiment, the techniques may be realized as an apparatus for ion implantation including a cooling device for cooling a target material to a predetermined temperature, and an ion implanter for implanting the target material with a carbon-containing species at the predetermined temperature to improve at least one of strain and amorphization.