Patents by Inventor Gary E. Hall

Gary E. Hall has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9070684
    Abstract: An integrated circuit power grid is provided with improved routing resources and bypass capacitance. A power grid for an integrated circuit comprises a plurality of thick metal layers having a plurality of metal traces, wherein at least one of the thick metal layers has a lower pitch than a substantial maximum pitch allowed under the design rules for a given integrated circuit fabrication technology. A power grid for an integrated circuit can also comprise a plurality of thin metal layers having a plurality of metal traces, wherein a plurality of the metal traces on different thin metal layers are connected by at least one via, wherein the at least one via is substantially surrounded by a metal trace on at least one thin metal level connected to a different power supply voltage than a power supply of one or more additional thin metal levels. The via can be positioned, for example, at an intersection of a given standard cell row and a given vertical strap.
    Type: Grant
    Filed: April 30, 2012
    Date of Patent: June 30, 2015
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Scott A. Segan, Scott T. Van Horn, Gary E. Hall, Matthew J. Gehman, Richard Muscavage
  • Publication number: 20130285219
    Abstract: An integrated circuit power grid is provided with improved routing resources and bypass capacitance. A power grid for an integrated circuit comprises a plurality of thick metal layers having a plurality of metal traces, wherein at least one of the thick metal layers has a lower pitch than a substantial maximum pitch allowed under the design rules for a given integrated circuit fabrication technology. A power grid for an integrated circuit can also comprise a plurality of thin metal layers having a plurality of metal traces, wherein a plurality of the metal traces on different thin metal layers are connected by at least one via, wherein the at least one via is substantially surrounded by a metal trace on at least one thin metal level connected to a different power supply voltage than a power supply of one or more additional thin metal levels. The via can be positioned, for example, at an intersection of a given standard cell row and a given vertical strap.
    Type: Application
    Filed: April 30, 2012
    Publication date: October 31, 2013
    Applicant: LSI CORPORATION
    Inventors: Scott A. Segan, Scott T. Van Horn, Gary E. Hall, Matthew J. Gehman, Richard Muscavage
  • Patent number: 6695794
    Abstract: A light weight, wearable, and balanced active tremor control system including a mount; a proof mass frame moveable with respect to the mount; at least one actuator on the proof mass frame for imparting a force on the mount; a motion sensor for detecting movement of the mount due to tremors; and a controller for driving the actuator in response to the motion sensor.
    Type: Grant
    Filed: February 12, 2002
    Date of Patent: February 24, 2004
    Assignee: The Charles Stark Draper Laboratory, Inc.
    Inventors: Kenneth W. Kaiser, Gary E. Hall
  • Publication number: 20030006357
    Abstract: A light weight, wearable, and balanced active tremor control system including a mount; a proof mass frame moveable with respect to the mount; at least one actuator on the proof mass frame for imparting a force on the mount; a motion sensor for detecting movement of the mount due to tremors; and a controller for driving the actuator in response to the motion sensor.
    Type: Application
    Filed: February 12, 2002
    Publication date: January 9, 2003
    Inventors: Kenneth W. Kaiser, Gary E. Hall