Abstract: An electrical signal pathway compatibility is negotiated between a first reconfigurable circuit module and a second, connected, reconfigurable circuit module. The first reconfigurable circuit module includes a circuit board, a programmable device possessing a plurality of programmable input/output pins, a connector, a plurality of electrical signal pathways, a first embedded controller, whereby the plurality of electrical signal pathways and the connector constitute a first pinout, and a second reconfigurable circuit module. The second reconfigurable circuit module includes a second embedded controller and a second pinout. A request for configuration signal is transmitted from the first embedded controller to the second embedded controller. A compatibility analysis is performed between the first pinout and the second pinout using said second embedded controller. An approval signal is transmitted from the second embedded controller to the first embedded controller.

Abstract: A reconfigurable circuit module comprises edge connectors for connecting with other reconfigurable circuit modules to form multi-dimensional arrays. Programmable devices such as FPGAs, CPLDs, etc. residing on the reconfigurable circuit modules control electric signal path functionality. An embedded controller microprocessor negotiates signal path compatibility between adjacent modules, preventing two or more programmable devices from simultaneously driving the same signal path.

Abstract: A reconfigurable circuit module comprises edge connectors for connecting with other reconfigurable circuit modules to form multi-dimensional arrays. Programmable devices such as FPGAs, CPLDs, etc. residing on the reconfigurable circuit modules control electric signal path functionality. An embedded controller microprocessor negotiates signal path compatibility between adjacent modules, preventing two or more programmable devices from simultaneously driving the same signal path.

Abstract: A digital storage medium for use with a computer system for producing a Dynamic Object Model interposed between FPGA hardware (including hardware platforms and FPGAs) and software applications. Hardware functional units are represented by unique Dynamic Objects. Dynamic Objects allow functional units to abstractly advertise their functionality and attributes directly to software applications as objects. Software applications can utilize these abstract functions and set functional unit attributes without specific knowledge of the physical composition of FPGA hardware. A Dynamic Object Model includes a software environment front end program component and a hardware environment back end program component. Additionally, a Dynamic API allows the front end program component to effectively communicate with the back end program component.

Abstract: A digital storage medium for use with a computer system for producing a Dynamic Object Model interposed between FPGA hardware (including hardware platforms and FPGAs) and software applications. Hardware functional units are represented by unique Dynamic Objects. Dynamic Objects allow functional units to abstractly advertise their functionality and attributes directly to software applications as objects. Software applications can utilize these abstract functions and set functional unit attributes without specific knowledge of the physical composition of FPGA hardware. A Dynamic Object Model includes a software environment front end program component and a hardware environment back end program component. Additionally, a Dynamic API allows the front end program component to effectively communicate with the back end program component.