Patents by Inventor Gary F. Besinga
Gary F. Besinga has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10915395Abstract: Various examples are directed to systems and methods for reading a memory component. A processing device may receive an indication that a read operation at a physical address of the memory component failed. The processing device may execute a plurality of read retry operations at the physical address. The processing device may access a first syndrome weight describing a first error correction operation performed on a result of a first read retry operation of the plurality of read retry operations and a second syndrome weight describing a second error correction operation performed on a result of a second read retry operation of the plurality of read retry operations. The processing device may select a first threshold voltage associated with the first read retry operation based at least in part on the first syndrome weight and the second syndrome weight.Type: GrantFiled: November 16, 2018Date of Patent: February 9, 2021Assignee: Micron Technology, Inc.Inventors: Ting Luo, Kishore Kumar Muchherla, Harish Reddy Singidi, Xiangang Luo, Renato Padilla, Jr., Gary F. Besinga, Sampath Ratnam, Vamsi Pavan Rayaprolu
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Publication number: 20200387324Abstract: A processing device in a memory system determines sensitivity value of a memory page in the memory system. The processing device assigns the memory page to a sensitivity tier of a plurality of sensitivity tiers based on a corresponding sensitivity value, wherein each sensitivity tier has a corresponding range of sensitivity values. The processing device further determines a targeted scan interval for each sensitivity tier of the plurality of sensitivity tiers and scans a subset of a plurality of memory pages in the memory component, wherein the subset comprises a number of memory pages from each sensitivity tier determined according to the corresponding targeted scan interval of each sensitivity tier.Type: ApplicationFiled: June 5, 2019Publication date: December 10, 2020Inventors: Kishore Kumar Muchherla, Gary F. Besinga, Cory M. Steinmetz, Pushpa Seetamraju, Jiangang Wu, Sampath K. Ratnam, Peter Feeley
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Patent number: 10854305Abstract: An indication of an initialization of power to a memory component can be received. In response to receiving the indication of the initialization, a last written page of a data block of the memory component can be identified. The last written page is associated with a status indicator. A determination is made of whether the status indicator is readable. Responsive to determining that the status indicator readable, it can be determined that programming of data to the data block of the memory component did complete and there is a data retention loss.Type: GrantFiled: March 16, 2020Date of Patent: December 1, 2020Assignee: MICRON TECHNOLOGY, INC.Inventors: Michael G. Miller, Kishore Kumar Muchherla, Harish R. Singidi, Walter Di Francesco, Renato C. Padilla, Gary F. Besinga, Violante Moschiano
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Publication number: 20200335172Abstract: Disclosed in some examples, are methods, systems, and machine readable mediums which compensate for read-disturb effects by shifting the read voltages used to read the value in a NAND cell based upon a read counter. For example, the NAND memory device may have a read counter that corresponds to a group of NAND cells (e.g., a page, a block, a superblock). Anytime a NAND cell in the group is read, the read counter may be incremented. The read voltage, Vread, may be adjusted based on the read counter to account for the read disturb voltage.Type: ApplicationFiled: July 2, 2020Publication date: October 22, 2020Inventors: Harish Reddy Singidi, Kishore Kumar Muchherla, Gianni Stephen Alsasua, Ashutosh Malshe, Sampath Ratnam, Gary F. Besinga, Micheal G. Miller
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Patent number: 10770156Abstract: A memory device comprising a main memory and a controller operably connected to the main memory is provided. The main memory can comprise a plurality of memory addresses, each corresponding to a single one of a plurality of word lines. Each memory address can be included in a tracked subset of the plurality of memory addresses. Each tracked subset can include memory addresses corresponding to more than one of the plurality of word lines. The controller is configured to track a number of read operations for each tracked subset, and to scan, in response to the number of read operations for a first tracked subset exceeding a first threshold value, a portion of data corresponding to each word line of the first tracked subset to determine an error count corresponding to each word line of the first tracked subset.Type: GrantFiled: May 18, 2019Date of Patent: September 8, 2020Assignee: Micron Technology, Inc.Inventors: Renato C. Padilla, Jung Sheng Hoei, Michael G. Miller, Roland J. Awusie, Sampath K. Ratnam, Kishore Kumar Muchherla, Gary F. Besinga, Ashutosh Malshe, Harish R. Singidi
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Patent number: 10755792Abstract: Disclosed in some examples, are methods, systems, and machine readable mediums which compensate for read-disturb effects by shifting the read voltages used to read the value in a NAND cell based upon a read counter. For example, the NAND memory device may have a read counter that corresponds to a group of NAND cells (e.g., a page, a block, a superblock). Anytime a NAND cell in the group is read, the read counter may be incremented. The read voltage, Vread, may be adjusted based on the read counter to account for the read disturb voltage.Type: GrantFiled: June 21, 2019Date of Patent: August 25, 2020Assignee: Micron Technology, Inc.Inventors: Harish Reddy Singidi, Kishore Kumar Muchherla, Gianni Stephen Alsasua, Ashutosh Malshe, Sampath Ratnam, Gary F. Besinga, Michael G. Miller
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Publication number: 20200219573Abstract: An indication of an initialization of power to a memory component can be received. In response to receiving the indication of the initialization, a last written page of a data block of the memory component can be identified. The last written page is associated with a status indicator. A determination is made of whether the status indicator is readable. Responsive to determining that the status indicator readable, it can be determined that programming of data to the data block of the memory component did complete and there is a data retention loss.Type: ApplicationFiled: March 16, 2020Publication date: July 9, 2020Inventors: Michael G. Miller, Kishore Kumar Muchherla, Harish R. Singidi, Walter Di Francesco, Renato C. Padilla, Gary F. Besinga, Violante Moschiano
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Publication number: 20200160894Abstract: A variety of applications can include apparatus and/or methods of operating the apparatus that include a memory device having read levels that can be calibrated. A calibration controller implemented with the memory device can trigger a read level calibration based on inputs from one or more trackers monitoring parameters associated with the memory device and a determination of an occurrence of at least one event from a set of events related to the monitored parameters. The monitored parameters can include parameters related to a selected time interval and measurements of read, erase, or write operations of the memory device. Additional apparatus, systems, and methods are disclosed.Type: ApplicationFiled: January 22, 2020Publication date: May 21, 2020Inventors: Kishore Kumar Muchherla, Ashutosh Malshe, Harish Reddy Singidi, Gianni Stephen Alsasua, Gary F. Besinga, Sampath Ratnam, Peter Sean Feeley
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Publication number: 20200159447Abstract: Various examples are directed to systems and methods for reading a memory component. A processing device may receive an indication that a read operation at a physical address of the memory component failed. The processing device may execute a plurality of read retry operations at the physical address. The processing device may access a first syndrome weight describing a first error correction operation performed on a result of a first read retry operation of the plurality of read retry operations and a second syndrome weight describing a second error correction operation performed on a result of a second read retry operation of the plurality of read retry operations. The processing device may select a first threshold voltage associated with the first read retry operation based at least in part on the first syndrome weight and the second syndrome weight.Type: ApplicationFiled: November 16, 2018Publication date: May 21, 2020Inventors: Ting Luo, Kishore Kumar Muchherla, Harish Reddy Singidi, Xiangang Luo, Renato Padilla, JR., Gary F. Besinga, Sampath Ratnam, Vamsi Pavan Rayaprolu
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Publication number: 20200090767Abstract: Several embodiments of memory devices and systems with offset memory component automatic calibration error recovery are disclosed herein. In one embodiment, a system includes at least one memory region and calibration circuitry. The memory region has memory cells that read out data states in response to application of a current read level signal. The calibration circuitry is operably coupled to the at least one memory region and is configured to determine a read level offset value corresponding to one or more of a plurality of offset read level test signals, including a base offset read level test signal. The base offset read level test signal is offset from the current read level signal by a predetermined value. The calibration circuitry is further configured to output the determined read level offset value.Type: ApplicationFiled: November 21, 2019Publication date: March 19, 2020Inventors: Bruce A. Liikanen, Gerald L. Cadloni, Gary F. Besinga, Michael G. Miller, Renato C. Padilla
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Patent number: 10593412Abstract: An indication of an initialization of power to a memory component can be received. In response to receiving the indication of the initialization, a last written page of a data block of the memory component can be identified. The last written page is associated with a status indicator. A determination is made of whether the status indicator can be read. Responsive to determining that the status indicator cannot be read, it can be determined that programming of data to the data block of the memory component did not complete based on a prior loss of power to the memory component.Type: GrantFiled: July 19, 2018Date of Patent: March 17, 2020Assignee: Micron Technology, Inc.Inventors: Michael G. Miller, Kishore Kumar Muchherla, Harish R. Singidi, Walter Di Francesco, Renato C. Padilla, Gary F. Besinga, Violante Moschiano
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Patent number: 10579307Abstract: Devices and techniques for correcting for power loss in NAND memory devices are disclosed herein. The NAND memory devices may comprise a number of physical pages. For example, a memory controller may detect a power loss indicator at the NAND flash memory. The memory controller may identify a last-written physical page and determine whether the last-written physical page comprises more than a threshold number of low-read-margin cells. If the last-written physical page comprises more than the threshold number of low-read-margin cells, the memory controller may provide a programming voltage to at least the low-read-margin cells.Type: GrantFiled: September 10, 2019Date of Patent: March 3, 2020Assignee: Micron Technology, Inc.Inventors: Michael G. Miller, Kishore Kumar Muchherla, Harish Reddy Singidi, Sampath Ratnam, Renato Padilla, Jr., Gary F. Besinga, Peter Sean Feeley
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Patent number: 10573357Abstract: A variety of applications can include apparatus and/or methods of operating the apparatus that include a memory device having read levels that can be calibrated. A calibration controller implemented with the memory device can trigger a read level calibration based on inputs from one or more trackers monitoring parameters associated with the memory device and a determination of an occurrence of at least one event from a set of events related to the monitored parameters. The monitored parameters can include parameters related to a selected time interval and measurements of read, erase, or write operations of the memory device. Additional apparatus, systems, and methods are disclosed.Type: GrantFiled: December 21, 2018Date of Patent: February 25, 2020Assignee: Micron Technology, Inc.Inventors: Kishore Kumar Muchherla, Ashutosh Malshe, Harish Reddy Singidi, Gianni Stephen Alsasua, Gary F. Besinga, Sampath Ratnam, Peter Sean Feeley
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Publication number: 20200027514Abstract: An indication of an initialization of power to a memory component can be received. In response to receiving the indication of the initialization, a last written page of a data block of the memory component can be identified. The last written page is associated with a status indicator. A determination is made of whether the status indicator can be read. Responsive to determining that the status indicator cannot be read, it can be determined that programming of data to the data block of the memory component did not complete based on a prior loss of power to the memory component.Type: ApplicationFiled: July 19, 2018Publication date: January 23, 2020Inventors: Michael G. Miller, Kishore Kumar Muchherla, Harish R. Singidi, Walter Di Francesco, Renato C. Padilla, Gary F. Besinga, Violante Moschiano
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Publication number: 20200020407Abstract: Disclosed in some examples, are methods, systems, and machine readable mediums which compensate for read-disturb effects by shifting the read voltages used to read the value in a NAND cell based upon a read counter. For example, the NAND memory device may have a read counter that corresponds to a group of NAND cells (e.g., a page, a block, a superblock). Anytime a NAND cell in the group is read, the read counter may be incremented. The read voltage, Vread, may be adjusted based on the read counter to account for the read disturb voltage.Type: ApplicationFiled: June 21, 2019Publication date: January 16, 2020Inventors: Harish Reddy Singidi, Kishore Kumar Muchherla, Gianni Stephen Alsasua, Ashutosh Malshe, Sampath Ratnam, Gary F. Besinga, Michael G. Miller
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Patent number: 10529433Abstract: Several embodiments of memory devices and systems with offset memory component automatic calibration error recovery are disclosed herein. In one embodiment, a system includes at least one memory region and calibration circuitry. The memory region has memory cells that read out data states in response to application of a current read level signal. The calibration circuitry is operably coupled to the at least one memory region and is configured to determine a read level offset value corresponding to one or more of a plurality of offset read level test signals, including a base offset read level test signal. The base offset read level test signal is offset from the current read level signal by a predetermined value. The calibration circuitry is further configured to output the determined read level offset value.Type: GrantFiled: August 13, 2018Date of Patent: January 7, 2020Assignee: Micron Technology, Inc.Inventors: Bruce A. Liikanen, Gerald L. Cadloni, Gary F. Besinga, Michael G. Miller, Renato C. Padilla
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Publication number: 20200004465Abstract: Devices and techniques for correcting for power loss in NAND memory devices are disclosed herein. The NAND memory devices may comprise a number of physical pages. For example, a memory controller may detect a power loss indicator at the NAND flash memory. The memory controller may identify a last-written physical page and determine whether the last-written physical page comprises more than a threshold number of low-read-margin cells. If the last-written physical page comprises more than the threshold number of low-read-margin cells, the memory controller may provide a programming voltage to at least the low-read-margin cells.Type: ApplicationFiled: September 10, 2019Publication date: January 2, 2020Inventors: Michael G. Miller, Kishore Kumar Muchherla, Harish Reddy Singidi, Sampath Ratnam, Renato Padilla, JR., Gary F. Besinga, Peter Sean Feeley
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Patent number: 10510422Abstract: Several embodiments of memory devices and systems with read level calibration are disclosed herein. In one embodiment, a memory device includes a controller operably coupled to a main memory having at least one memory region and calibration circuitry. The calibration circuitry is operably coupled to the at least one memory region and is configured to determine a read level offset value corresponding to a read level signal of the at least one memory region. In some embodiments, the calibration circuitry is configured to obtain the read level offset value internal to the main memory. The calibration circuitry is further configured to output the read level offset value to the controller.Type: GrantFiled: September 10, 2018Date of Patent: December 17, 2019Assignee: Micron Technology, Inc.Inventors: Gary F. Besinga, Peng Fei, Michael G. Miller, Roland J. Awusie, Kishore Kumar Muchherla, Renato C. Padilla, Harish R. Singidi, Jung Sheng Hoei, Gianni S. Alsasua
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Publication number: 20190370099Abstract: Apparatus having an array of memory cells include a controller configured to read a particular memory cell of a last written page of memory cells of a block of memory cells of the array of memory cells, determine whether a threshold voltage of the particular memory cell is less than a particular voltage level, and mark the last written page of memory cells as affected by power loss during a programming operation of the last written page of memory cells when the threshold voltage of the particular memory cell is determined to be higher than the particular voltage level.Type: ApplicationFiled: August 19, 2019Publication date: December 5, 2019Applicant: MICRON TECHNOLOGY, INC.Inventors: Michael G. Miller, Ashutosh Malshe, Violante Moschiano, Peter Feeley, Gary F. Besinga, Sampath K. Ratnam, Walter Di-Francesco, Renato C. Padilla, JR., Yun Li, Kishore Kumar Muchherla
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Patent number: 10446197Abstract: A variety of applications can include apparatus and/or methods of operating the apparatus that include a memory device having read levels that can be calibrated. A calibration controller implemented with the memory device can trigger a read level calibration based on inputs from one or more trackers monitoring parameters associated with the memory device and a determination of an occurrence of at least one event from a set of events related to the monitored parameters. The monitored parameters can include parameters related to a selected time interval and measurements of read, erase, or write operations of the memory device. Additional apparatus, systems, and methods are disclosed.Type: GrantFiled: August 31, 2017Date of Patent: October 15, 2019Assignee: Micron Technology, Inc.Inventors: Kishore Kumar Muchherla, Ashutosh Malshe, Harish Singidi, Gianni Stephen Alsasua, Gary F. Besinga, Sampath Ratnam, Peter Sean Feeley