Abstract: One example relates to a device that includes an activity monitor. The activity monitor includes a bus interface having inputs coupled to receive signals from a bus and having outputs coupled to provide signals to an other device. The activity monitor monitors the bus for a message directed to a predefined address that is associated with the other device in response to detecting that the other device is a low power sleep mode, the activity monitor outputs the predefined address to the other device to enable the other device to capture the predefined address, via the bus interface, in response to the monitored address matching the predefined address that is associated with the other device.

Abstract: A power circuit includes a switch circuit, an auxiliary load circuit coupled to an output terminal, a switching control circuit to operate the switch circuit responsive to an error signal, a regulator circuit having a sense resistor, a comparator to provide the error signal, and a DAC to control a sense current of the sense resistor. A DAC control circuit provides a DAC input signal having a controlled ramp rate responsive to a decreasing setpoint signal, a load control circuit selectively enables the auxiliary load circuit responsive to the decreasing setpoint signal and responsive to the error signal to control the power circuit slew rate.

Abstract: One example relates to a device that includes an activity monitor. The activity monitor includes a bus interface having inputs coupled to receive signals from a bus and having outputs coupled to provide signals to an other device. The activity monitor monitors the bus for a message directed to a predefined address that is associated with the other device in response to detecting that the other device is a low power sleep mode, the activity monitor outputs the predefined address to the other device to enable the other device to capture the predefined address, via the bus interface, in response to the monitored address matching the predefined address that is associated with the other device.

Abstract: An inductor has first and second terminals. A first switch is coupled between the first terminal and a voltage supply terminal. A second switch is coupled between the first terminal and a negative output supply terminal. A third switch is coupled between the second terminal and a positive output supply terminal. A fourth switch is coupled between the second terminal and a ground terminal. A controller is coupled to the first, second, third and fourth switches. The controller is configured to provide: an inductor charge mode; a positive boost mode; a negative boost mode; a first rest state in which the controller closes the first switch and opens the second, third and fourth switches; and a second rest state in which the controller closes the fourth switch and opens the first, second and third switches.

Abstract: One example relates to a device that includes an activity monitor. The activity monitor includes a bus interface having inputs coupled to receive signals from a bus and having outputs coupled to provide signals to an other device. The activity monitor monitors the bus for a message directed to a predefined address that is associated with the other device in response to detecting that the other device is a low power sleep mode, the activity monitor outputs the predefined address to the other device to enable the other device to capture the predefined address, via the bus interface, in response to the monitored address matching the predefined address that is associated with the other device.

Abstract: A circuit includes a phase-locked loop having a phase-locked loop output to provide a first phase signal and a second phase signal phase delayed with respect to the first phase signal. The circuit further includes a digital circuit having a digital circuit input and an output. The digital circuit input couples to the phase-locked loop output. On the digital circuit output, the digital circuit is configured to provide a first digital-to-analog converter (DAC) enable signal and a second DAC enable signal. The circuit also includes first and second DACs. The first DAC is coupled to the digital circuit. The first DAC has a first enable input coupled to the digital circuit output to receive the first DAC enable signal. The second DAC is coupled to the digital circuit. The second DAC has a second enable input coupled to the digital circuit output to receive the second DAC enable signal.

Abstract: A power circuit includes a switch circuit, an auxiliary load circuit coupled to an output terminal, a switching control circuit to operate the switch circuit responsive to an error signal, a regulator circuit having a sense resistor, a comparator to provide the error signal, and a DAC to control a sense current of the sense resistor. A DAC control circuit provides a DAC input signal having a controlled ramp rate responsive to a decreasing setpoint signal, a load control circuit selectively enables the auxiliary load circuit responsive to the decreasing setpoint signal and responsive to the error signal to control the power circuit slew rate.

Abstract: An inductor has first and second terminals. A first switch is coupled between the first terminal and a voltage supply terminal. A second switch is coupled between the first terminal and a negative output supply terminal. A third switch is coupled between the second terminal and a positive output supply terminal. A fourth switch is coupled between the second terminal and a ground terminal. A controller is coupled to the first, second, third and fourth switches. The controller is configured to provide: an inductor charge mode; a positive boost mode; a negative boost mode; a first rest state in which the controller closes the first switch and opens the second, third and fourth switches; and a second rest state in which the controller closes the fourth switch and opens the first, second and third switches.

Abstract: A circuit includes a phase-locked loop having a phase-locked loop output to provide a first phase signal and a second phase signal phase delayed with respect to the first phase signal. The circuit further includes a digital circuit having a digital circuit input and an output. The digital circuit input couples to the phase-locked loop output. On the digital circuit output, the digital circuit is configured to provide a first digital-to-analog converter (DAC) enable signal and a second DAC enable signal. The circuit also includes first and second DACs. The first DAC is coupled to the digital circuit. The first DAC has a first enable input coupled to the digital circuit output to receive the first DAC enable signal. The second DAC is coupled to the digital circuit. The second DAC has a second enable input coupled to the digital circuit output to receive the second DAC enable signal.

Abstract: One example relates to a device that includes an activity monitor. The activity monitor includes a bus interface having inputs coupled to receive signals from a bus and having outputs coupled to provide signals to an other device. The activity monitor monitors the bus for a message directed to a predefined address that is associated with the other device in response to detecting that the other device is a low power sleep mode, the activity monitor outputs the predefined address to the other device to enable the other device to capture the predefined address, via the bus interface, in response to the monitored address matching the predefined address that is associated with the other device.

Abstract: A system includes an inductor and a first switch coupled between a first end of the inductor and a voltage supply node. The system also includes a second switch coupled between the first end of the inductor and a negative output supply node. The system also includes a third switch coupled between a second end of the inductor and a positive output supply node. The system also includes a fourth switch coupled between the second end of the inductor and a ground node. The system also includes a controller coupled to the first, second, third, and fourth switches. The controller is configured to provide an inductor charge mode, a positive boost mode, a negative boost mode, a first rest state involving the first switch, and a second rest state involving the fourth switch.

Abstract: One example relates to a device that includes an activity monitor. The activity monitor includes a bus interface having inputs coupled to receive signals from a bus and having outputs coupled to provide signals to an other device. The activity monitor monitors the bus for a message directed to a predefined address that is associated with the other device in response to detecting that the other device is a low power sleep mode, the activity monitor outputs the predefined address to the other device to enable the other device to capture the predefined address, via the bus interface, in response to the monitored address matching the predefined address that is associated with the other device.

Abstract: A system includes an inductor and a first switch coupled between a first end of the inductor and a voltage supply node. The system also includes a second switch coupled between the first end of the inductor and a negative output supply node. The system also includes a third switch coupled between a second end of the inductor and a positive output supply node. The system also includes a fourth switch coupled between the second end of the inductor and a ground node. The system also includes a controller coupled to the first, second, third, and fourth switches. The controller is configured to provide an inductor charge mode, a positive boost mode, a negative boost mode, a first rest state involving the first switch, and a second rest state involving the fourth switch.

Abstract: One example relates to a device that includes an activity monitor. The activity monitor includes a bus interface having inputs coupled to receive signals from a bus and having outputs coupled to provide signals to an other device. The activity monitor monitors the bus for a message directed to a predefined address that is associated with the other device in response to detecting that the other device is a low power sleep mode, the activity monitor outputs the predefined address to the other device to enable the other device to capture the predefined address, via the bus interface, in response to the monitored address matching the predefined address that is associated with the other device.

Abstract: A method of decoding a biphase mark coded (BMC) data stream. A BMC encoded signal (BMC signal) including a preamble and data payload is received at a receiver which includes a BMC decoder state machine (state machine). The preamble is processed using the state machine including measuring a total duration spanning at least three transitions to provide a ?2 UI duration measure, a calculated 0.75 UI duration value (0.75 UI duration value) is generated from the ?2 UI duration measure, and the 0.75 UI duration value is compared to a programmed UI range. Provided the 0.75 UI duration value is within the programmed UI range data, respective bits are extracted bit-by-bit from the data payload using the 0.75 UI duration value to obtain unencoded data.

Abstract: A method of decoding a biphase mark coded (BMC) data stream. A BMC encoded signal (BMC signal) including a preamble and data payload is received at a receiver which includes a BMC decoder state machine (state machine). The preamble is processed using the state machine including measuring a total duration spanning at least three transitions to provide a ?2 UI duration measure, a calculated 0.75 UI duration value (0.75 UI duration value) is generated from the ?2 UI duration measure, and the 0.75 UI duration value is compared to a programmed UI range. Provided the 0.75 UI duration value is within the programmed UI range data, respective bits are extracted bit-by-bit from the data payload using the 0.75 UI duration value to obtain unencoded data.

Abstract: A digital circuit may have at least two asynchronous clock domains with a controller responsive to a first domain clock signal and a target responsive to a second domain clock signal. A first domain control signal pulse is generated in response to the first domain clock signal for controlling the target. Each assertion the first domain control signal pulse is detected and used to form a second domain control signal pulse synchronized to the second domain clock signal. The target is controlled using the second domain control signal pulse. If the target is a clear-on-read register, contents of the clear-on-read register are latched in a feedback register in response to the first domain control signal pulse and provided to the controller. Each bit of the clear-on-read register is reset in response to the second domain control signal pulse only if the corresponding latched content of each bit in the feedback register is a logical one.

Abstract: A digital circuit may have at least two asynchronous clock domains with a controller responsive to a first domain clock signal and a target responsive to a second domain clock signal. A first domain control signal pulse is generated in response to the first domain clock signal for controlling the target. Each assertion the first domain control signal pulse is detected and used to form a second domain control signal pulse synchronized to the second domain clock signal. The target is controlled using the second domain control signal pulse. If the target is a clear-on-read register, contents of the clear-on-read register are latched in a feedback register in response to the first domain control signal pulse and provided to the controller. Each bit of the clear-on-read register is reset in response to the second domain control signal pulse only if the corresponding latched content of each bit in the feedback register is a logical one.

Abstract: A system for presenting serial drive signals for effecting communication of parallel data signals includes: a controller; a serializer coupled with the controller; and a tri-state logic device coupled with the serializer. The controller provides parallel logic state signals to the serializer. The serializer treats the parallel data signals to present a serial data signal representing the parallel data signals at a first output locus, and treats the parallel logic state signals to present a serial logic state signal representing the parallel logic state signals at a second output locus. The tri-state logic device receives the serial data signal and the serial logic state signal for logical evaluation. The tri-state logic device presents the serial drive signals at a third output locus. Each respective drive signal has a respective drive state. Each respective drive state is determined by the logical evaluation.