Patents by Inventor Gary Giust

Gary Giust has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230184828
    Abstract: An apparatus and method for analyzing phase noise in a signal. A plurality of signal samples, each signal sample representing a value of phase noise in a signal-under-test at a corresponding offset frequency, and filter data representing filter characteristics on a first side of a spectrum boundary, are used to derive filtered signal samples. A measure of noise is derived from the filtered signal samples. This abstract is not to be considered limiting, since other embodiments may deviate from the features described in this abstract.
    Type: Application
    Filed: February 10, 2023
    Publication date: June 15, 2023
    Applicant: JitterLabs LLC
    Inventor: Gary Giust
  • Patent number: 11592480
    Abstract: An apparatus and method for analyzing phase noise in a signal. A plurality of signal samples, each signal sample representing a value of phase noise in a signal-under-test at a corresponding offset frequency, and filter data representing filter characteristics on a first side of a spectrum boundary, are used to derive filtered signal samples. A measure of noise is derived from the filtered signal samples. This abstract is not to be considered limiting, since other embodiments may deviate from the features described in this abstract.
    Type: Grant
    Filed: December 27, 2021
    Date of Patent: February 28, 2023
    Assignee: JitterLabs LLC
    Inventor: Gary Giust
  • Publication number: 20220120810
    Abstract: An apparatus and method for analyzing phase noise in a signal. A plurality of signal samples, each signal sample representing a value of phase noise in a signal-under-test at a corresponding offset frequency, and filter data representing filter characteristics on a first side of a spectrum boundary, are used to derive filtered signal samples. A measure of noise is derived from the filtered signal samples. This abstract is not to be considered limiting, since other embodiments may deviate from the features described in this abstract.
    Type: Application
    Filed: December 27, 2021
    Publication date: April 21, 2022
    Applicant: JitterLabs LLC
    Inventor: Gary Giust
  • Patent number: 11231459
    Abstract: An apparatus and method for analyzing phase noise in a signal. A plurality of signal samples, each signal sample representing a value of phase noise in a signal-under-test at a corresponding offset frequency, and filter data representing filter characteristics on a first side of a spectrum boundary, are used to derive filtered signal samples. A measure of noise is derived from the filtered signal samples. This abstract is not to be considered limiting, since other embodiments may deviate from the features described in this abstract.
    Type: Grant
    Filed: October 6, 2020
    Date of Patent: January 25, 2022
    Assignee: JitterLabs LLC
    Inventor: Gary Giust
  • Publication number: 20210033670
    Abstract: An apparatus and method for analyzing phase noise in a signal. A plurality of signal samples, each signal sample representing a value of phase noise in a signal-under-test at a corresponding offset frequency, and filter data representing filter characteristics on a first side of a spectrum boundary, are used to derive filtered signal samples. A measure of noise is derived from the filtered signal samples. This abstract is not to be considered limiting, since other embodiments may deviate from the features described in this abstract.
    Type: Application
    Filed: October 6, 2020
    Publication date: February 4, 2021
    Applicant: JitterLabs LLC
    Inventor: Gary Giust
  • Patent number: 10802074
    Abstract: An apparatus and method for analyzing phase noise in a signal. A plurality of signal samples, each signal sample representing a value of phase noise in a signal-under-test at a corresponding offset frequency, and filter data representing filter characteristics on a first side of a spectrum boundary, are used to derive filtered signal samples. A measure of noise is derived from the filtered signal samples. This abstract is not to be considered limiting, since other embodiments may deviate from the features described in this abstract.
    Type: Grant
    Filed: December 5, 2018
    Date of Patent: October 13, 2020
    Assignee: JITTERLABS LLC
    Inventor: Gary Giust
  • Publication number: 20190204386
    Abstract: An apparatus and method for analyzing phase noise in a signal. A plurality of signal samples, each signal sample representing a value of phase noise in a signal-under-test at a corresponding offset frequency, and filter data representing filter characteristics on a first side of a spectrum boundary, are used to derive filtered signal samples. A measure of noise is derived from the filtered signal samples. This abstract is not to be considered limiting, since other embodiments may deviate from the features described in this abstract.
    Type: Application
    Filed: December 5, 2018
    Publication date: July 4, 2019
    Applicant: JitterLabs LLC
    Inventor: Gary Giust
  • Patent number: 7388440
    Abstract: A lock-aid circuit and method is applied to a phase lock loop (PLL) having a voltage controlled oscillator (VCO), wherein the lock aid is coupled with the input of the VCO. In one example, the lock aid includes a Schmitt trigger having an output, a switch having an output and an input coupled to the output of the Schmitt trigger, and a voltage controlled current source coupled with the output of the switch.
    Type: Grant
    Filed: December 2, 2004
    Date of Patent: June 17, 2008
    Assignee: Cypress Semiconductor Corp.
    Inventors: Gary Giust, Chwei-Po Chew, Sung-Ki Min
  • Patent number: 6162714
    Abstract: A method is provided for forming thin polysilicon transistor gates using dual doped polysilicon without reducing the ion implant energy. The method comprises depositing polysilicon over a region of a substrate, masking and implanting the polysilicon with dopant impurities to form the channel regions of one conductivity type, and removing the photo resist mask. The polysilicon layer is then masked to define the channel regions of the opposite conductivity type and is implanted with dopant impurities of the opposite conductivity type. Following the dual ion implantation, the photo resist mask is removed and the substrate may be annealed to activate the dopants in the polysilicon. The dual doped polysilicon layer is then polished using a chemical-mechanical polish to achieve a desired thickness for the polysilicon transistor gates. The polysilicon is subsequently masked and etched to define the polysilicon transistor gates.
    Type: Grant
    Filed: December 16, 1997
    Date of Patent: December 19, 2000
    Assignee: LSI Logic Corporation
    Inventors: Ruggero Castagnetti, Yauh-Ching Liu, Gary Giust, Subramanian Ramesh