Abstract: A system and method for resolving three-state busses while generating a compact vector set which will detect as many stuck-at faults as possible. Two passes are made through the circuit design. In the first pass, all three-state busses in the design are satisfied at the same time to eliminate conflicts on all of the busses and the ordered pairs of inputs for resolving the bus are saved. In the second pass, a primary fault is targeted and a sequence is generated to detect the fault and is saved for later reference. Then secondary faults are targeted to find input sets that will detect the secondary faults and if such inputs will also satisfy all of the three-state busses, the primary inputs for the secondary fault are saved.